sy58023u Micrel Semiconductor, sy58023u Datasheet - Page 4

• Manufacturer Part Number: sy58023u
• Description: Sy58023u 10.7gbps 2 X 2 Crosspoint Switch W/cml Outputs And Internal Termination
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
V
Symbol
V
V
V
R
Notes:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established
V
Symbol
f
t
t
t
t
Notes:
7.
8.
9.
10. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
11. Total jitter definition: With an ideal clock input of frequency ≤ f
12. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps–3.2Gbps.
13. Deterministic jitter is measured at 2.5Gbps–3.2Gbps with both K28.5 and 2
14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while
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MAX
pd
SKEW
JITTER
r
, t
CC
OH
OUT
DIFF_OUT
OUT
CC
CML OUTPUT DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
f
= +3.3V ±10% or +2.5V ±5%; R
Measured with 100mV input swing. High frequency AC-parameters are guaranteed by design and characterization.
Skew is measured between outputs of the same bank under identical transitions.
Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
signal.
the specified peak-to-peak jitter value.
applying similar, differential clock frequencies that are asynchronous with respect to each other at inputs.
= 2.5V ±5% or 3.3V ±10%; R
Parameter
Output HIGH Voltage
Output Voltage Swing
Differential Voltage Swing
Output Source Impedance
Parameter
Maximum Operating Frequency
Propagation Delay
Channel-to-Channel Skew
(Within Bank)
Part-to-Part Skew
Clock
Data
Output Rise/Fall Time
Crosstalk Induced Jitter
Cycle-to-Cycle Jitter
(Adjacent Channel)
Deterministic Jitter
L
= 100Ω across each output pair; T
L
Random Jitter
= 100Ω across each output pair; T
Total Jitter
Condition
Q0, /Q0; Q1, /Q1
Q0, /Q0; Q1, /Q1; see Figure 1a.
Q0, /Q0; Q1, /Q1; see Figure 1b.
Q0, /Q0; Q1, /Q1
Condition
V
IN-to-Q
SEL-to-Q
Note 8
Note 9
Note 10
Note 11
Note 12
Note 13
Note 14
20% to 80%, at full swing.
IN
(7)
≥ 100mV; V
MAX
, no more than one output edge in 10
4
A
OUT
= –40°C to +85°C, unless otherwise stated.
23
A
–1 PRBS pattern.
= –40°C to +85°C, unless otherwise stated.
≥ 200mV
(6)
n
–T
n–1
where T is the time between rising edges of the output
NRZ Data
Clock
12
V
output edges will deviate by more than
CC
Min
325
650
–0.020
40
10.7
Min
135
100
25
6
Typ
400
800
Typ
50
Precision Edge
1000
Max
Max
V
500
285
400
0.7
60
20
75
10
10
60
1
1
CC
SY58023U
ps
ps
ps
Units
Units
Gbps
ps
ps
GHz
mV
mV
ps
ps
ps
ps
ps
Ω
V
RMS
RMS
RMS
PP
PP
®