max9205eait Maxim Integrated Products, Inc., max9205eait Datasheet - Page 7

• Manufacturer Part Number: max9205eait
• Description: 10-bit, Bus Lvds Serializers
• Manufacturer: Maxim Integrated Products, Inc.

Bypass AV
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AV
quency surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DV
Output trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100Ω termination, the
output swing is larger.
Figure 1. Output Voltage Definitions
Figure 3. Input Clock Transition Time Requirement
Differential Traces and Termination
CC
Applications Information
OUT+
OUT-
with high-frequency surface-mount
_______________________________________________________________________________________
V
CC
OD
Power-Supply Bypassing
. Bypass DV
R
R
2
2
L
L
TCLK
V
OS
CC
10%
with high-fre-
90%
t
CLKT
10-Bit Bus LVDS Serializers
CC
.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90° turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
Figure 2. Worst-Case I
EVEN IN_
ODD IN_
TCLK
t
CLKT
90%
10%
TCLK_R/F = LOW
0
3V
CC
Test Pattern
7