max9208eait Maxim Integrated Products, Inc., max9208eait Datasheet
max9208eait
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max9208eait Summary of contents
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Rev 1; 12/07 General Description The MAX9206/MAX9208 deserializers transform a high- speed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with seri- alizers such as the MAX9205/MAX9207, which ...
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Bus LVDS Deserializers ABSOLUTE MAXIMUM RATINGS AGND, DGND .................................-0. RI+, RI- to AGND, DGND .........................................-0.3V to +4V All Other Pins to DGND ..............................-0. ROUT_ Short-Circuit Duration (Note 1) ......................Continuous ...
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AC ELECTRICAL CHARACTERISTICS ( +3.0V to +3.6V 15pF, differential input voltage 2. -40°C to +85°C, unless otherwise noted. Typical values are ...
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Bus LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (continued) ( +3.0V to +3.6V 15pF, differential input voltage 2. -40°C to +85°C, unless otherwise noted. Typical ...
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PIN NAME 1, 12, 13 AGND Analog Ground Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of ...
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Bus LVDS Deserializers IN2 V - 0.3V CC RI+ R IN1 R IN1 RI- Figure 2. Input Fail-Safe Circuit START SYMBOL N BIT RCLK ROUT_ Figure 4. Input-to-Output Delay RCLK RCLK_R/F = ...
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PWRDN REFCLK t RFCP RI t ZHLK LOCK HIGH-Z RCLK HIGH-Z ROUT_ HIGH-Z 2048 x t Figure 7. PLL Lock Time from PWRDN REFCLK t RFCP RI LOCK RCLK ROUT_ Figure 8. Deserializer PLL Lock Time from Sync Patterns _______________________________________________________________________________________ ...
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Bus LVDS Deserializers Detailed Description The MAX9206/MAX9208 deserialize a BLVDS serializ- er's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial ...
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Table 1. Typical Lock Times REFCLK 16MHz FREQUENCY DATA PSEUDORANDOM PATTERN DATA Maximum 0.749µs Maximum (Clock 11.99 Cycles) Average 0.318µs Average (Clock 5.09 Cycles) Minimum 0.13µs Minimum (Clock 2.08 Cycles) Note: Pseudorandom lock performed with PRBS pattern, ...
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Bus LVDS Deserializers t /12 RCP Figure 9. Input Jitter Tolerance Applications Information Power-Supply Bypassing Bypass each supply pin with high-frequency surface- mount ceramic 0.1µF and 0.001µF capacitors in paral- lel as close to the ...
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Table 2. Input/Output Function Table LOGIC INPUTS CONDITIONS PWRDN REN X Low Power applied and stable Low High Deserializer initialized High High Deserializer initialized X = don’t care The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of ...
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Bus LVDS Deserializers NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2007 Maxim Integrated Products 10-Bit Bus LVDS Deserializers DESCRIPTION is a registered trademark of Maxim Integrated Products, Inc. Revision History PAGES CHANGED — ...