max9316aewp-t Maxim Integrated Products, Inc., max9316aewp-t Datasheet
max9316aewp-t
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max9316aewp-t Summary of contents
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... Part-to-Part Skew at +25°C o 20ps Output-to-Output Skew o 365ps Propagation Delay o Synchronous Output Enable/Disable o On-Chip Reference for Single-Ended Inputs o Input Biased to Low when Open o Pin Compatible with MC100EL14 Applications PART MAX9316AEWP TOP VIEW RECEIVER 50Ω Features Ordering Information TEMP RANGE PIN-PACKAGE -40°C to +85°C ...
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Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS ...............................................................................6. Single-Ended Inputs (SCLK, SEL, EN, CLK, CLK) ≤ 4.2V.........................V For For > 4.2V ........................V ...
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DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 5.5V, outputs loaded with 50Ω ± values are 5.0V IHD PARAMETER SYMBOL CONDITIONS Differential Input V ...
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Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS ( 3.0V to 5.5V, outputs are loaded with 50Ω ± (20% to 80%), SEL = high or low low, V ...
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1V IHD CC ILD 50Ω 2V +25°C, unless otherwise noted SUPPLY CURRENT vs.TEMPERATURE 40 ALL PINS ARE OPEN EXCEPT V AND V ...
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Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver PIN NAME 1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor Inverting Q0 Output. Typically terminate with 50Ω resistor Noninverting Q1 Output. Typically ...
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For interfacing to differential (LV)ECL, the V -3.0V to -5.5V (with V grounded). Output levels are CC referenced to V and are considered (LV)PECL or CC ...
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Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver CLK CLK Q_ Q_ Figure 1. MAX9316A Switching Characteristics with Single-Ended Input CLK CLK Figure 2. MAX9316A Timing Diagram 8 _______________________________________________________________________________________ ...
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SCLK Figure 3. MAX9316A Timing Diagram for SCLK CLK SCLK OR CLK Q_ OUTPUTS ARE LOW Q_ EN Timing Diagram Figure 4. MAX9316A _______________________________________________________________________________________ 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver ...
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Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver 45kΩ 45kΩ CLK CLK 30kΩ 45kΩ 45kΩ SCLK 30kΩ SEL ______________________________________________________________________________________ ...
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