max9325eqit Maxim Integrated Products, Inc., max9325eqit Datasheet

max9325eqit

Manufacturer Part Number

max9325eqit

Description

Max9325 2 8 Differential Lvpecl/lvecl/hstl Clock And Data Driver

Manufacturer

Maxim Integrated Products, Inc.

Datasheet

1.MAX9325EQIT.pdf (12 pages)

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The MAX9325 low-skew, 2:8 differential driver features

extremely low output-to-output skew (50ps max) and

part-to-part skew (225ps max). These features make

the device ideal for clock and data distribution across a

backplane or board. The device selects one of the two

differential HSTL or LVECL/LVPECL inputs and repeats

them at eight differential outputs. Outputs are compati-

ble with LVECL and LVPECL, and can directly drive

50Ω terminated transmission lines.

The differential inputs can be configured to accept a

single-ended signal when the unused complementary

input is connected to the on-chip reference output volt-

age V

ensure differential low default outputs when the inputs

are left open or at V

The MAX9325 operates over a 2.375V to 3.8V supply

range for interfacing to differential HSTL and LVPECL

signals. This allows high-performance clock or data dis-

tribution in systems with a nominal +2.5V or +3.3V sup-

ply. For LVECL operation, the device operates with a

-2.375V to -3.8V supply.

The MAX9325 is offered in 28-lead PLCC and space-

saving 28-lead QFN packages. The MAX9325 is speci-

fied for operation from -40°C to +85°C.

19-2511; Rev 3; 11/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EE.

2:8 Differential LVPECL/LVECL/HSTL Clock and

CLK_SEL

CLKO

TOP VIEW

CLK1

The internal pulldowns and a fail-safe circuit

BB.

Precision Clock Distribution

Low-Jitter Data Repeaters

All inputs have internal pulldown resistors to

________________________________________________________________ Maxim Integrated Products

MAX9325

PLCC

General Description

Applications

CLK_SEL

CLKO

CLK1

*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V

♦ 50ps (max) Output-to-Output Skew

♦ 1.5ps

♦ Guaranteed 300mV Differential Output at 700MHz

♦ +2.375V to +3.8V Supplies for Differential

♦ -2.375V to -3.8V Supplies for Differential LVECL

♦ Two Selectable Differential Inputs

♦ On-Chip Reference for Single-Ended Inputs

♦ Outputs Low for Inputs Open or at V

♦ Pin Compatible with MC100LVE310

Functional Diagram appears at end of data sheet.

MAX9325EQI

MAX9325EGI

MAX9325

HSTL/LVPECL

QFN

PART

RMS

(max) Random Jitter

-40°C to +85°C

TEMP RANGE

Ordering Information

Pin Configurations

CLK_SEL

Data Driver

INPUT SELECT TRUTH TABLE

CLK0, CLK0 SELECTED

CLK1, CLK1 SELECTED

PIN-PACKAGE

28 PLCC

28 QFN 5mm x 5mm

INPUT CLOCK

Features

Related parts for max9325eqit

max9325eqit Summary of contents

Page 1

Rev 3; 11/04 2:8 Differential LVPECL/LVECL/HSTL Clock and General Description The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution ...

Page 2

Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS ...............................................................-0.3V to +4. CLK_, CLK_SEL Inputs (CLK_, ......-0. CLK_ to CLK_ .....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA V ...

Page 3

Differential LVPECL/LVECL/HSTL Clock and DC ELECTRICAL CHARACTERISTICS (continued) (( 2.375V to 3.8V 50Ω ± (Notes 1–4) PARAMETER SYMBOL CONDITIONS Differential Input V Figure 1 ILD Low Voltage (V ...

Page 4

Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS—PLCC Package (( 2.375V to 3.8V 50Ω ± are 3.3V ...

Page 5

Differential LVPECL/LVECL/HSTL Clock and AC ELECTRICAL CHARACTERISTICS—QFN Package (( 2.375V to 3.8V 50Ω ± are 3.3V 1V), V ...

Page 6

Differential LVPECL/LVECL/HSTL Clock and Data Driver (PLCC package, typical values are at (V 500MHz, input transition time = 125ps (20% to 80%).) SUPPLY CURRENT (I vs. TEMPERATURE -40 -15 10 TEMPERATURE (°C) ...

Page 7

Differential LVPECL/LVECL/HSTL Clock and PIN NAME PLCC QFN 11, 18 CLK0 CLK1 CLK1 N. ...

Page 8

Differential LVPECL/LVECL/HSTL Clock and Data Driver IHD ILD IHD ILD V EE DIFFERENTIAL INPUT VOLTAGE DEFINITION Figure 1. Input Voltage Definitions CLK CLK Q_ Q_ DIFFERENTIAL OUTPUT WAVEFORM ...

Page 9

Differential LVPECL/LVECL/HSTL Clock and CLK_ WHEN CLK_ = CLK_ WHEN CLK_ = Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram Detailed Description The MAX9325 low-skew, 2:8 differential ...

Page 10

Differential LVPECL/LVECL/HSTL Clock and Data Driver ferential input is configured for single-ended operation by connecting the on-chip reference voltage, V unused complementary input as a reference. For exam- ple, the differential CLK0, CLK0 input is converted to a noninverting, ...

Page 11

Differential LVPECL/LVECL/HSTL Clock and (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages NOTES: ...

Page 12

Differential LVPECL/LVECL/HSTL Clock and Data Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other ...

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