nb6vq572m ON Semiconductor, nb6vq572m Datasheet - Page 6

• Manufacturer Part Number: nb6vq572m
• Description: 1.8v / 2.5v Differential 4 1 Mux W/input Equalizer To 1 2 Cml Clock/data Fanout / Translator
• Manufacturer: ON Semiconductor

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to V
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
Table 6. AC CHARACTERISTICS
f
f
f
V
t
t
t
t
t
F
t
t
V
t
MAX
DATAMAX
SEL
PLH
PHL
PD Tempco
skew
DC
JITTER
r,
Symbol
OUTPP
FN
INPP
, t
N
40 ps (20% − 80%).
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
inputs.
f
,
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Maximum Input Clock Frequency
Maximum Operating Data Rate
Maximum Toggle Frequency, SELx
Output Voltage Amplitude (@ V
Propagation Delay to Differential
Outputs Measured at Differential
Crosspoint
Differential Propagation Delay Temperature Coefficient
Output − Output skew (within device) (Note 13)
Device − Device skew (t
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
Phase Noise, f
Integrated Phase Jitter (Figure TBD) f
Offset (RMS)
Random Clock Jitter, RJ (Note 14)
Deterministic Jitter, DJ (Note 15)
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Falltimes @ 1 GHz; (20% − 80%), V
in
= 1 GHz
pdmax
V
Characteristic
CC
= 1.71 V to 2.625 V, GND = 0 V, T
− t
INPPmin
pdmin
in
)
) (Note 12) (Figure 12)
= 1 GHz, 12 kHz − 20 MHz
@ 1 GHz INx/INx to Qx/Qx
@ 50 MHz SELx to Qx
http://onsemi.com
f
in
≤ 6.5 Gbps (12” FR4)
IN
= 400 mV Qx, Qx
V
NRZ, (PRBS23)
OUT
6
f
IN
f
f
w 250 mV
in
in
v 5 GHz
≤ 5 GHz
≤ 5 GHz
100 kHz
10 kHz
10 MHz
20 MHz
40 MHz
1 MHz
A
= −40°C to +85°C (Note 11)
Min
250
100
100
6.5
45
25
5
4
−135
−136
−149
−150
−150
−151
Typ
400
175
0.2
10
50
30
50
35
45
6
8
7
0
CC
1200
Max
250
100
0.8
0.7
20
15
55
10
65
. Input edge rates
ps pk−pk
ps RMS
ps RMS
Dfs/°C
Gbps
MHz
Unit
GHz
dBc
mV
mV
ps
ns
ps
ps
%
fs