sky73134-11 Skyworks Solutions, Inc., sky73134-11 Datasheet - Page 4

• Manufacturer Part Number: sky73134-11
• Description: Sky73134-11 Wideband Pll Frequency Synthesizer
• Manufacturer: Skyworks Solutions, Inc.

PRELIMINARY DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Lock Detect
The lock detect circuit is activated when the phase difference
between the Up and Dn phase detector signals for a given number
of comparison cycles is shorter than a fixed delay. The CMOS
output is active high when the loop is locked.
Bidirectional Digital Interface
A three-wire Serial Programmable Interface (SPI) with read/write
capability provides mode and bias control, and control of the PLL.
The serial interface consists of three signals: the bus clock (CLK),
latch enable (LE), and the serial, bidirectional data line (DATA).
Write Mode. A write data stream consists of 25 bits:
Read Mode. The read data stream is almost identical to the write
data stream. Following the 5-bit register address, a “turn around”
cycle is inserted so the baseband can disable its drive of the data
4
Bits[15:0] provide the 16-bit data block.
Bits[20:16] provide the register address.
Bit[21] is the read/write bit (0 = read, 1 = write).
Bits[24:22] provide the device address (the SKY73134-11 is
011b).
DATA
DATA
CLK
CLK
LE
LE
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
A7
A7
July 7, 2010 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201199C
A6
A6
A5
A5
Write
Read
R/W
R/W
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
Around
Turn-
D15 D14 D13 D12 D11 D10
D15 D14 D13 D12 D11 D10
Figure 3. Read/Write SPI Cycles
line and the addressed device on the bus can activate its data
output driver.
When the baseband addresses a device connected to the serial
bus, the bus enable signal (LE) goes low half a clock cycle before
the CLK signal becomes active. Data on the DATA line is clocked
into the SKY73134-11 on the rising edge of the clock.
Data from the SKY73134-11 to the baseband is clocked at the
falling edge of the clock. The enable line goes high at the end of
the data transfer. The clock becomes inactive one clock pulse
after the enable signal goes high. The CLK signal is always
disabled for at least one equivalent cycle between subsequent
accesses.
A timing diagram for the SPI read/write cycle is shown in
Figure 3.
Serial Bus Timing
The SPI bus speed is programmable. Timing requirements for the
CLK, DATA, and LE signals are provided in Table 2. A serial data
input timing diagram is shown in Figure 4.
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
A7
A7
A6
A6
S348