sky73112-11 Skyworks Solutions, Inc., sky73112-11 Datasheet - Page 10

• Manufacturer Part Number: sky73112-11
• Description: Sky73112-11 750-850 Mhz High Performance Vco/synthesizer With Integrated Switch
• Manufacturer: Skyworks Solutions, Inc.

DATA SHEET • SKY73112-11 VCO/SYNTHESIZER
Lock Detect
Lock detection circuitry provides a CMOS logic level indication
when the PLL is frequency locked (high when locked). Normally,
pin 22 (LD) is used for lock detect output. This pin can also be
programmed as the R1 divider output, N-divider output, or DPLL
test output. Pin 22 is controlled by Word 0, bits [17:15].
Reference Input Divider
The R-counter (reference input clock divider) consists of three
divide-by-two blocks and one multiplexer controlled by the
rdiv[3:2] parameter in Word 2. The R1 divider is used to select a
divide-by-one, two, four, or divide-by-eight function.
The integral loop filter (see Figure 1) is designed to operate at an
internal comparison frequency of approximately 6.5 MHz. The
input reference signal must be divided using the rdiv [3:2] bits in
Word 2 to closely match this frequency. Further optimization of
the loop filter bandwidth may be accomplished using the
cp_output [4:2] bits in Word 0.
Reference Buffer Bandwidth
The two-bit parameter ref_bw_sel adjusts the operating point of
the input buffer to compensate for different reference signal
sources. Generally the best setting is 50 MHz, but this could vary
depending on the source used.
Synthesizer Output Switch
An on-chip switch is integrated into the SKY73112-11 RF output
after the balun and is controlled by the SW_EN signal (pin 4) as
indicated below:
The switch provides >50 dB isolation at the synthesizer RF
output. This allows the SKY73112-11 to be used for GSM
applications.
Synthesizer Programming
To program the synthesizer to the correct frequency, values for
the N-counter (both M and A portions), fractional divisor (FN), and
fractional modulus extender (ME) are needed. These values are
used to determine the total divider ratio, D
Equation 1:
Where: N
10
FN
ME
actual
actual
actual
SW_EN Input
= the actual value of the N-counter
D
High
Low
= the actual fractional divisor
= the actual fractional modulus extender
Total
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
November 30, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200736B
= N
actual
+ FN
actual
+ ME
Synthesizer Output
Total
actual
, according to
+ 3.5
On
Off
(1)
Because of the way the
SKY73112-11, the number 3.5 must be added to the division
number to obtain the final division ratio.
The calculated value for D
correct synthesizer frequency, RF:
Where: F
The 6-bit M-counter and the 4-bit A-counter portions of the N-
counter are calculated according to the following relationships:
N
(D
If:
Then: N = M
Where: N is the number to be programmed into the N-counter.
The synthesizer has a selectable prescaler of 8/9 or 16/17. If the
16/17 prescaler is used:
In this case, N is the same as N
N
If the 8/9 prescaler is used:
Here, N is not equal to N
three LSBs (the 4
NOTE: The minimum actual N counter value for the 8/9 mode is
The fractional divisor code (FN) sets the fractional-N modulo up to
256 modulo according to the following equation:
The value of FN is equal to the binary representation of 256 (or 2
The fractional modulo can be extended up to 2
extender (ME) if required:
actual
actual
Total
FN
ME
actual
, and A is equal to the four LSBs of N
– 3.5):
is the actual N-counter value and is the integer portion of
actual
FN
8 x 7 = 56, and for the 16/17 mode is 16 x 15 = 240.
M = M
A = A
R1 = the reference divider radio
, or:
REF
actual
P = 2
P = 8
= D
= the reference frequency
FN = D
actual
actual
×
14
4
(1/2
D
2
= 16
(binary number, fit to four bits)
th
7
4
(binary number, fit to six bits)
+ A
bit of the A-counter is a “don’t care” bit).
7
9
1
2
N
) + D
actual
2
actual
RF
7
D
13
+ D
Total
= M
6
(1/2
modulator is implemented in the
. The A-counter portion only uses the
2
1
can then be used to determine the
6
F
2
actual
REF
R1
10
actual
) + D
2
×
6
D
, M is equal to the six MSBs of
+ D
5
D
P + A
12
Total
2
1
(1/2
5
3
actual
actual
2
11
5
) + . . . + D
+ . . . D
.
23
using the modulo
D
0
0
2
0
1
(1/2
8
23
)
(2)
(3)
(4)
8
)