sky73112-11 Skyworks Solutions, Inc., sky73112-11 Datasheet - Page 3

• Manufacturer Part Number: sky73112-11
• Description: Sky73112-11 750-850 Mhz High Performance Vco/synthesizer With Integrated Switch
• Manufacturer: Skyworks Solutions, Inc.

Technical Description
The SKY73112-11 is a fractional-N frequency synthesizer using a
provides low in-band noise by having a low division and fast
frequency settling time. The device also provides programmable,
arbitrary fine frequency resolution. This compensates the
frequency synthesizer for crystal frequency drift.
Serial I/O Control Interface
The SKY73112-11 is programmed through a three-wire serial bus
control interface using four 26-bit words. The three-wire interface
consists of three signals: CLK (pin 17), LE (pin 19), and the bit
serial data line DATA (pin 18). The convention is to load data from
the most significant bit to the least significant bit (MSB to LSB). A
serial data input timing diagram is shown in Figure 3. Preset
timing parameter values are provided in Table 2.
Although the SKY73112-11 uses a 5 V DC supply, the internal
voltage regulator has a 3.3 V output for the PLL. Therefore, the
input DC voltage for the serial interface (CLK, DATA, and LE
signals) should be set to 3.3 V or lower.
Figure 4 depicts the serial bus, which consists of one 26-bit load
register and four separate 24-bit registers. Data is initially clocked
into the load register starting with the MSB and ending with the
LSB. The LE signal is used to gate the clock to the load register,
requiring the LE signal to be brought low before the data load.
Data is shifted on the rising edge of CLK.
The two final LSBs are decoded to determine which holding
register should latch the data. The falling edge of LE latches the
data into the appropriate holding register. This programming
sequence must be repeated to fill all four holding registers.
The specific hold register addresses are determined by the wd_0
and wd_1 parameters in the load register. These are the two
LSBs (bits [1:0]) as shown in Figure 4. Table 3 lists the four hold
registers and their respective addresses as determined in the load
register.
The contents of each word in the load register are used to
program the four hold registers described in Tables 4 through 7.
modulation technique. The fractional-N implementation
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
DATA
200736B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2009
CLK
LE
Figure 3. SKY73112-11 Serial Data Input Timing Diagram (MSB First)
t
DSU
t
DHD
The dpll_ctrl parameter (bits [19:2] of Word 1) programs the
Digital Phase Locked Loop (DPLL) block. Each of the 18 bits that
comprise the dpll_ctrl parameter map directly to the signal ports
on the DPLL block as shown in Table 8 (except for the
dpll_flag_override and dpll_flag_value parameters).
Loading new data into a holding register not associated with the
synthesizer frequency programming does not reset or change the
synthesizer. The synthesizer should not lose lock before, during,
or after a new serial word load that does not change the
programmed frequency.
VCO Auto-Tuning Loop
A VCO auto-tuning loop provides the proper 7-bit coarse tuning
setting for the VCO switch capacitors in the VCO output. This sets
the oscillation frequency as close to target as possible before
starting fine analog tuning.
When VCO auto-tuning is enabled, the PLL performs a seven-step
successive approximation process to digitally tune the VCO close
to the final programmed frequency. Once that is complete, analog
tuning is switched in to lock the VCO to the programmed
frequency.
The auto-tuning loop is designed to compensate process variation
so that the VCO fine tuning range can be reduced to cover
temperature variation only. It significantly reduces VCO gain (Kv)
which reduces VCO phase noise.
There are two conditions that enable the VCO auto-tuning
function: a Power-On-Reset (POR) and a change in frequency. The
difference in the program flow under each of these conditions is
illustrated in Figure 5. Under either condition, dpll_en (bit [20] of
Word 1) should first be cleared so that a rising edge pulse can be
generated. Following this pulse, set dpll_en to enable VCO auto-
tuning.
A POR timing diagram is shown in Figure 6. VCO auto-tuning
details in the frequency and time domains are shown in Figure 7.
t
CKH
t
CKL
DATA SHEET • SKY73112-11 VCO/SYNTHESIZER
t
CLE
t
LEW
t
LEC
S1053
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