mc145145p2 Lansdale Semiconductor, Inc., mc145145p2 Datasheet - Page 6

• Manufacturer Part Number: mc145145p2
• Description: 4?bit Data Bus Input Pll Frequency Synthesizer
• Manufacturer: Lansdale Semiconductor, Inc.

ML145145
INPUT PINS
D0 – D3
Data Inputs (PDIP – Pins 2, 1, 18, 17; SOG – Pins 2, 1, 20, 19)
latches when the ST input is in the high state. D3 is most sig-
nigicant bit.
f in
Frequency Input (PDIP – Pin 3, SOG – Pin 4)
from the loop VCO and is ac couples. For larger amplitude sig-
nals (standard CMOS – logic levels) dc coupling may be used.
OSCin/OSCout
Reference Oscillator Input/Output (PDIP – Pins 6, 7; SOG
– Pins 7, 8)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as input for an externally–generated reference
signal. This signal is typically AC coupled to OSC in but for
larger amplitude signals (standard CMOS–logic levels) DC
coupling may also be used. In the external refrence mode, no
connection is required to OSC out .
A0 – A2
Address Inputs (PDIP – Pins 8, 9, 10; SOG – Pins 9, 10, 12)
information on the data input lines. The addresses refer to the
following latches:
ST
Strobe Transfer (PDIP – Pin 11, SOG – Pin 13)
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Information at these inputs is transferred to the internal
Input to ÷N portion of synthesizer. f in is typically derived
These pins form an on–chip reference oscillator when con-
A0, A1 and A2 are used to define which latch receives the
The rising edge of strobe transfers data into the addressed
PIN DESCRIPTIONS
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latch, the falling edge of strobe latches data into the latch. This
pin should normally be held low to avoid loading latches with
invalid data.
OUTPUT PINS
PDout
Single–Ended Phase Detector output (PDIP – Pin 12, SOG
– Pin 14)
signal.
LD
Lock Detector Signal (PDIP – Pin 13, SOG – Pin 15)
frequency). Pulses low when loop is out of lock.
φV, φR
Phase Detect or Outputs (PDIP – Pin 12, SOG – Pin 14)
a loop–error signal. A single–ended output is also available for
this purpose (see PD out ).
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
provided reference–input signal.
POWER SUPPLY PINS
V SS
Ground (PDIP – Pin 4, SOG – Pin 5)
V DD
Positive Power Supply (PDIP – Pin 5, SOG – Pin 6)
with respect to V SS .
Three–state output of phase detector for use as loop–error
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Impedance
High level when loop is locked (f R , f V of same phase and
These phase detector outputs can be combined externally for
If frequency f V is greater than f R or if the phase of f V is
If the frequency of f V – f R and both are in phase, then both
REF out
Buffered Reference Output (DIP – Pin 16, SOG – Pin 18)
Buffered output of on–chip reference oscillator or externally
Circuit Ground
The positive supply voltage may range from 3.0 to 9.0 V
State
LANSDALE Semiconductor, Inc.
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