z84c00 ZiLOG Semiconductor, z84c00 Datasheet
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Z84C90 KIO Serial/Parallel Counter Timer Product Specification PS011802-0902 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • http://www.ZiLOG.com ...
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This publication is subject to replacement by a later edition. To determine whether a later edition exists request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Windows ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1. KIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1. Z84C90 KIO Serial/Parallel/Counter/TimerPackages . . . . . . . . . . . . . . . . . . 1 Table 2. KIO Registers . . . . . . . . . ...
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... PLCC or 100-pin LQFP). Using fifteen internal registers for data and programming information, the KIO can easily be configured to any given system environment. Although the optimum performance is obtained with a Z84C00 CPU, the KIO can just as easily be used with any other CPU. ...
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OSC XTAL 1 Oscillator XTAL 0 CLKOUT Bus MI Interface RD and IORQ Control RESET CLK INT Interrupt IE1 Control IE0 Figure 1. KIO Block Diagram PS011802-0902 KIO Serial/Parallel Counter Timer ...
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Absolute Maximum Ratings Voltage Voltages on all inputs with respect Operating Ambient Temperature Storage Temperature Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This rating is ...
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Pin Types PC1 (SYNCB) 12 PC2 (DTRB) 13 PC3 (RTSB) 14 TxDA 15 TxCA 16 RxCA 17 RxDA 18 PA0 19 PA1 20 PA2 PA3 23 GND 24 PA4 25 PA5 26 PA6 27 PA7 28 ...
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PC0 (WT/RDYB) GND CSTA 80 DCDA DCDB CTSB TxDB TxCB 85 RxCB RxDB IORQ RESET CLK/TRG3 NC NC 100 1 Figure 3. 100-Pin LQFP Configuration ...
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Port B does not support Mode 2 operation and can only be used in Note: Mode 3 when Port A is programmed for Mode 2. BRDY is not associated with Port B when it is operating in Mode 3. ASTB, ...
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IEI. Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that no higher-priority device ...
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SIO channels disabled • Marking with interrupts disabled. All control registers must be rewritten after a hardware reset. RTSA, RTSB. Request to Send (outputs, Active Low). These signals are modem control signals for their serial channels. They follow the ...
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Table 2. KIO Registers Address Register 0: PIO Port A Data Register 1: PIO Port A Command Register 2: PIO Port B Data Register 3: PIO Port B Command Register 4: CTC Channel 0 Register 5: CTC Channel 1 Register ...
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The Ordering Information section lists temperature ranges and product numbers. Package drawings are in the Package Information section. Refer to the Literature List for additional documentation. From Output Under Test Figure 4. Test Load Diagram Data CPU Bus I/O Control ...
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Data Bus Figure 6. PIA Block Diagram Data 8 CPU Bus I/O Control 6 Figure 7. CTC Block Diagram PS011802-0902 KIO Serial/Parallel Counter Timer Port C PC0`PC7 Dir. Ctrl. Internal Bus Reset Z84C90 Internal Control Logic INT Interrupt IE1 Logic ...
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ZTALI Crystal Inputs XTALO Figure 8. Crystal Connection PS011802-0902 KIO Serial/Parallel Counter Timer C1 C2 Z84C90 12 ...
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Channel A Control and Status Registers Internal Control Logic Data 8 CPU Bus I/O Control 7 Interrupt Interrupt Control Control Lines Logic Channel B Control and Status Registers Figure 9. SIO Block Diagram PS011802-0902 KIO Serial/Parallel Counter Timer Channel A ...
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DC Characteristics V = 5.0V +/– 10% unless otherwise specified. cc Table 3. DC Characteristics of the Z84C90 Symbol Item V Clock Input Low Voltage ILC V Clock Input High Voltage IHC V Input Low Voltage IL V Input High ...
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AC Characteristics Table 5. AC Characteristics of the Z84C90 No. Symbol Parameter Bus Interface Timing 1 TcC Clock Cycle Time 2 TwCh Clock Pulse Width (High) 3 TwCl Clock Pulse Width (Low) 4 TfC Clock Fall Time 5 TrC Clock ...
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Table 5. AC Characteristics of the Z84C90 (Continued) No. Symbol Parameter 22 TsIEI(Cf) IEI to Clock Fall Setup (for 4D Decode) 23 TsIOr(Cf) IORQ Rise to Clock Fall Setup (to activate RDY on next clock) PIO Timing 24 TdCf(RDYr) Clock ...
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Table 5. AC Characteristics of the Z84C90 (Continued) No. Symbol Parameter 39 TdCTRr(INTf) CLK/TRG Rise to INT Fall Delay TsCTRr(Cr) satisfied TsCTRr(Cr) not satisfied 40 TcCTR CLK/TRG Cycle Time 41 TwCTRh CLK/TRG Width High 42 TwCTRI CLK/TRG Width Low 43 ...
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Table 5. AC Characteristics of the Z84C90 (Continued) No. Symbol Parameter 63 TrRxC RxC Rise Time 64 TfRxC RxC Fall Time 65 TsRxD(RxCr) RxD to RxC Rise Setup 66 ThRxCr(RxD) RxC Rise to RxD Hold Time 67 TdRxCr(W/Rf) RxC Rise ...
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Table 6.Daisy Chain Parameters (Continued) No. Symbol Parameter 2 19 TsIEI (IO) (PIO at #3) (CTC at #3) (SIO at # TdIEI(IEOf TdIEI(IEOr) Notes: to calculate Z80 KIO daisy-chain timing, use the Z80 PIO, CTC, and ...
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Clock 2 3 A0– IORQ 6 RD D0–D7 RD D0–D7 WT/RDY Wait Mode 48 WT/RDY Ready Mode Figure 10. I/O Read/Write Timing ( PS011802-0902 KIO Serial/Parallel Counter Timer ...
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CTS DCD SYNC TxC TxD WT/RDY INT RxC RxD WT/RDY INT SYNC Figure 11. Serial I/O Timing PS011802-0902 KIO Serial/Parallel Counter Timer ...
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Clock CLK/TRG Counter 37 CLK/TRG Timer 38 ZC/TO 39 INT Figure 12. Counter/Timer Timing PS011802-0902 KIO Serial/Parallel Counter Timer Z84C90 ...
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Clock IORQ RD 34 Port C Input Port C Output RDY STB Mode 0 Mode 1 Mode 2 Mode 3 INT Figure 13. Port I/O Read/Write Timing PS011802-0902 KIO Serial/Parallel Counter Timer Z84C90 24 25 ...
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T1 T2 Clock INT 16 M1 IORQ D – IE1 18 IE0 Figure 14. Interrupt Acknowledge Cycle Clock – IE1 20 21 IE0 Figure 15. Op Code Fetch Cycle PS011802-0902 KIO Serial/Parallel ...
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Precautions & Limitations The following describe the limitations of Revision A of the Z84C90 KIO. Problem: Daisy-chain. If the KIO has an Interrupt Pending during and Interrupt Acknowledge cycle, KIO misses the status of the IE1 pin. This produces vector ...
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Work Around: This problem could happen under the following narrowly defined conditions: • CE signal is active throughout the Interrupt Acknowledge cycle. • The address on the bus, A3–A0, is “110b”. • During this time, bit • ...