74lvc2t45

Manufacturer Part Number74lvc2t45
DescriptionDual Supply Translating Transceiver; 3-state
ManufacturerNXP Semiconductors
74lvc2t45 datasheet
 


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74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 02 — 5 February 2009
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V
and V
CC(B)
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to V
pins nB are referenced to V
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using I
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features
I
Wide supply voltage range:
N
V
N
V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8C (2.7 V to 3.6 V)
N
JESD36 (4.5 V to 5.5 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 4000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Maximum data rates:
N
420 Mbps (3.3 V to 5.0 V translation)
N
210 Mbps (translate to 3.3 V))
N
140 Mbps (translate to 2.5 V)
N
75 Mbps (translate to 1.8 V)
N
60 Mbps (translate to 1.5 V)
). Both V
and V
can be supplied at any voltage between 1.2 V and
CC(A)
CC(B)
. A HIGH on DIR allows transmission from nA to nB and a
CC(B)
: 1.2 V to 5.5 V
CC(A)
: 1.2 V to 5.5 V
CC(B)
Product data sheet
CC(A)
and
CC(A)
. The I
OFF
OFF
or V
are at
CC(A)
CC(B)

74lvc2t45 Summary of contents

  • Page 1

    ... Dual supply translating transceiver; 3-state Rev. 02 — 5 February 2009 1. General description The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V ...

  • Page 2

    ... Product data sheet 74LVC2T45; 74LVCH2T45 = 3 circuitry provides partial Power-down mode operation Description VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm XSON8 plastic extremely thin small outline package; no leads; ...

  • Page 3

    ... Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC2T45 74LVCH2T45 V 1 CC( GND 4 001aai904 Fig 3. Pin configuration SOT765-1 (VSSOP8) 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 CC(B) 001aag577 Fig CC( DIR Fig 4. Rev. 02 — 5 February 2009 Dual supply translating transceiver; 3-state ...

  • Page 4

    ... H = HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [3] When either GND level, the device goes into suspend mode. CC(A) CC(B) 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state terminal 1 index area 8 V CC( ...

  • Page 5

    ... V is the supply voltage associated with the output port. CCO [ the supply voltage associated with the input port. CCI 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Conditions V < < Active mode Suspend or 3-state mode ...

  • Page 6

    ... CCO [ the supply voltage associated with the data input port. CCI [3] To guarantee the node switches, an external driver must source/sink at least I 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 = 25 C amb Conditions ...

  • Page 7

    ... V CCO 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 [ 5.5 V [ ...

  • Page 8

    ... HIGH port BHHO overdrive V CCI current V CCI V CCI V CCI V CCI I OFF-state port output current 5.5 V CCO 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 …continued [ 1 4 1.4 V CCO = 1.65 V CCO = 2.3 V CCO = 3.0 V CCO = 4.5 V CCO = 5 [2] = 1.4 V CCI = 1.65 V CCI = 2.3 V CCI = 3.0 V CCI = 4 ...

  • Page 9

    ... CCO [ the supply voltage associated with the data input port. CCI [3] To guarantee the node switches, an external driver must source/sink at least I [4] For non bus hold parts only (74LVC2T45). 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 …continued 5 ...

  • Page 10

    ... OFF-state to HIGH PZH propagation delay t OFF-state to LOW PZL propagation delay [1] t and t are calculated values using the formula shown in PZH PZL 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 = 1.2 V and T CC(A) Figure Conditions 10.1 DIR to A 9.4 DIR ...

  • Page 11

    ... HIGH to LOW PHL propagation delay HIGH to OFF-state DIR to A PHZ propagation delay DIR LOW to OFF-state DIR to A PLZ propagation delay DIR to B 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 = V CC( where ns pF ...

  • Page 12

    ... HIGH to LOW PHL propagation delay HIGH to OFF-state DIR to A PHZ propagation delay DIR to B 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Figure 9; for wave forms see 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V Min Max Min Max [ ...

  • Page 13

    ... DIR LOW to OFF-state DIR to A PLZ propagation delay DIR OFF-state to HIGH DIR to A PZH propagation delay DIR to B 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Figure 9; for wave forms see 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V Min Max Min Max 1.4 3.7 1.4 3.7 2 ...

  • Page 14

    ... HIGH to OFF-state DIR to A PHZ propagation delay DIR LOW to OFF-state DIR to A PLZ propagation delay DIR to B 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Figure 9; for wave forms see 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V Min Max Min Max [ ...

  • Page 15

    ... HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. Enable and disable times 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Figure 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V Min Max Min Max [ ...

  • Page 16

    ... CC( CCI [ the supply voltage associated with the data input port. CCI [2] dV/dt 1.0 V/ns. [ the supply voltage associated with the output port. CCO 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 [1] [2] Output V M 0.5V CCO 0.5V CCO 0.5V CCO negative ...

  • Page 17

    ... HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 10. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 001aai907 14 t PLH (ns) 12 (1) 10 (2) 8 (3) (4) 6 (5) ( (pF ...

  • Page 18

    ... HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 11. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 001aai911 14 t PLH (ns (1) 8 (2) 6 (3) (4) 4 ( (pF ...

  • Page 19

    ... HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 12. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 001aai915 14 t PLH (ns (1) 8 (2) 6 (3) (4) 4 (5) ( (pF ...

  • Page 20

    ... HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 13. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 001aai919 14 t PLH (ns (1) 8 (2) 6 (3) 4 (4) (5) ( (pF ...

  • Page 21

    ... HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 14. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 001aai923 14 t PLH (ns (1) 8 (2) 6 (3) 4 (4) (5) ( (pF ...

  • Page 22

    ... HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 15. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 001aai927 14 t PLH (ns (1) 8 (2) 6 (3) 4 (4) (5) ( (pF ...

  • Page 23

    ... GND (LOW level) determines B port to A port direction input threshold value depends on V input threshold value depends on V supply voltage of system-2 (1 5.5 V) shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic Rev. 02 — 5 February 2009 Dual supply translating transceiver; 3-state V ...

  • Page 24

    ... NXP Semiconductors V CC1 I/O-1 PULL-UP/DOWN DIR CTRL system-1 Pull-up or pull-down only needed for 74LVC2T45. Fig 17. Bidirectional logic level-shifting application Table 17 and then from system-2 to system-1. Table 17. Description of bidirectional logic level-shifting application State DIR CTRL I/O output input [ HIGH voltage level ...

  • Page 25

    ... PZL In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74LVC2T45; 74LVCH2T45 initially is transmitting from then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specifi ...

  • Page 26

    ... Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT765-1 Fig 18. Package outline SOT765-1 (VSSOP8) 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 2.5 scale ...

  • Page 27

    ... UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT833 Fig 19. Package outline SOT833-1 (XSON8) 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 scale 1.05 0.35 0.40 ...

  • Page 28

    ... DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 20. Package outline SOT996-2 (XSON8U) 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 scale ...

  • Page 29

    ... DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC SOT902 Fig 21. Package outline SOT902-1 (XQFN8U) 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 scale ...

  • Page 30

    ... Revision history Table 20. Revision history Document ID Release date 74LVC_LVCH2T45_2 20090205 • Modifications: Added type numbers 74LVC2T45GD and 74LVCH2T45GD (XSON8U package) 74LVC_LVCH2T45_1 20081118 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Data sheet status Change notice Product data sheet ...

  • Page 31

    ... For more information, please visit: For sales office addresses, please send an email to: 74LVC_LVCH2T45_2 Product data sheet 74LVC2T45; 74LVCH2T45 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...

  • Page 32

    ... Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 19 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...