max5109 Maxim Integrated Products, Inc., max5109 Datasheet - Page 9

• Manufacturer Part Number: max5109
• Description: Max5109 Nonvolatile, Dual, 8-bit Dacs With 2-wire Serial Interface
• Manufacturer: Maxim Integrated Products, Inc.

The MAX5109 8-bit DACs feature internal, nonvolatile
registers that store the DAC states for initialization dur-
ing power-up. This device consists of resistor-string
DACs, rail-to-rail output buffers, a shift register, power-
on reset (POR) circuitry, and volatile and nonvolatile
memory registers (Figure 1). The shift register decodes
the control and address bits, routing the data to the
proper registers. Writing data to a selected volatile reg-
ister immediately updates the DAC outputs.
The volatile registers retain data as long as the device
is powered. Removing power clears the volatile regis-
ters. The nonvolatile registers retain data even after
power is removed. On startup, when power is first
applied, data from the nonvolatile registers is trans-
ferred to the volatile registers to automatically initialize
the device. Read data from the nonvolatile or volatile
registers using the 2-wire serial interface.
The MAX5109 uses a DAC matrix decoding architec-
ture that saves power. A resistor string divides the dif-
ference between the external reference voltages,
V
the appropriate tap from the resistor string, providing
the equivalent analog voltage. The resistor string pre-
sents a code-independent input impedance to the ref-
erence and guarantees a monotonic output. Figure 2
shows a simplified diagram of one DAC.
Figure 1. MAX5109 Functional Diagram
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
REFH_
and V
REFL_
_______________________________________________________________________________________
. Row and column decoders select
MUTE
Detailed Description
SDA
SCL
A3
A2
A1
A0
9
14
16
1
2
3
4
INTERFACE/
CONTROL
2-WIRE
SERIAL
MAX5109
POR
DAC Operation
NONVOLATILE
NONVOLATILE
REGISTER
REGISTER
DAC0
DAC1
GND
V
REGISTER
REGISTER
VOLATILE
VOLATILE
15
DD
8
DAC0
DAC1
The MAX5109 analog outputs are internally buffered by
precision unity-gain amplifiers. The outputs swing from
GND to V
The amplifier outputs typically settle to ±0.5 LSB in 8µs
when loaded with 5kΩ in parallel with 100pF.
Figure 2. DAC Simplified Circuit Diagram
D7
D6
D5
D4
DAC
DD
DAC0
DAC1
with a V
REFH_
R0
REFL_
Output Buffer Amplifiers
D3
13
12
11
-to-V
5
6
7
R1
D2
REFH0
REFL0
OUT0
REFH1
REFL1
OUT1
LSB DECODER
REFH_
D1
Interface
D0
output transition.
R255
R15
R16
REFL_
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