max5581aeupt Maxim Integrated Products, Inc., max5581aeupt Datasheet
max5581aeupt
Related parts for max5581aeupt
max5581aeupt Summary of contents
Page 1
Rev 3; 7/07 12-/10-/8-Bit, Voltage-Output DACs General Description The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage- output, digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog ...
Page 2
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS ........................................................................± AGND to DGND ..................................................................±0. AGND, DGND.............................................-0. AGND, DGND ............................................-0.3V to +6V DD FB_, OUT_, REF to AGND ........-0.3V ...
Page 3
Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF PARAMETER SYMBOL Power-Supply Rejection PSRR Ratio REFERENCE ...
Page 4
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF PARAMETER SYMBOL PU INPUT ...
Page 5
Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF PARAMETER SYMBOL POWER REQUIREMENTS Analog Supply Voltage ...
Page 6
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) ( 2.7V to 5.25V, AGND = DGND = MIN to T MAX , unless otherwise noted.) PARAMETER ...
Page 7
Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) ( 1.8V to 2.7V, AGND = DGND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width ...
Page 8
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) ( 2.7V to 5.25V, AGND = DGND = MIN to T MAX , unless otherwise noted.) PARAMETER ...
Page 9
Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) ( 1.8V to 2.7V, AGND = DGND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width ...
Page 10
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ( 5V 4.096V 10kΩ REF L INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5580A) 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 ...
Page 11
Voltage-Output DACs ( 5V 4.096V REF L INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (MAX5581A) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ...
Page 12
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ( 5V 4.096V 10kΩ REF L SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 100 UNITY GAIN 75 FORCE SENSE 70 65 ...
Page 13
Voltage-Output DACs ( 5V 4.096V REF L SETTLING TIME NEGATIVE MAX5580-85 toc28 FULL-SCALE TRANSITION CS 2V/div OUT_ 2V/div 400ns/div DAC-TO-DAC CROSSTALK MAX5580-85 toc31 OUTA–OUTC 2V/div OUTD 2mV/div 200µs/div ______________________________________________________________________________________ Buffered, Fast-Settling, ...
Page 14
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs PIN MAX5580 MAX5581 MAX5582 MAX5583 MAX5584 MAX5585 TSSOP THIN QFN TSSOP 17 15, 17 — — — — — ...
Page 15
Voltage-Output DACs SERIAL INTERFACE SCLK CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 POWER-DOWN LOGIC LOGIC AND REGISTER DECODE CONTROL PU INPUT REGISTER A INPUT REGISTER D REF ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, DV ...
Page 16
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs CS SERIAL INTERFACE SCLK CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 LOGIC DECODE CONTROL PU REF 16 ______________________________________________________________________________________ Functional Diagrams (continued AGND DD DD POWER-DOWN LOGIC AND REGISTER ...
Page 17
Voltage-Output DACs Detailed Description The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage- output DACs offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V ...
Page 18
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Table 1. Serial Write Data Format MSB CONTROL BITS D11 D10 SCLK DIN CS t CSW DOUTDC1* DOUTDC0 OR DOUTRB* *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR ...
Page 19
Voltage-Output DACs Serial-Interface Programming Commands Tables 2a, 2b, and 2c provide all the serial-interface programming commands for the MAX5580–MAX5585. Table 2a shows the basic DAC programming com- mands, Table 2b gives the advanced-feature program- ming commands, and Table 2c ...
Page 20
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 20 ______________________________________________________________________________________ ...
Page 21
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ______________________________________________________________________________________ 21 ...
Page 22
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 22 ______________________________________________________________________________________ ...
Page 23
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs D0/X D0/X D0/X D1/X D1/X D1/X D2/X D2/X D2/X D3/X D3/X D3 D10 D10 D10 D11 ...
Page 24
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5580–MAX5585 can load all the input registers ...
Page 25
Voltage-Output DACs Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdown- mode bits determine the output state of the selected channels. The shutdown-control bits put the selected channels into ...
Page 26
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 12. To read back the settling-time-mode bits, use the com- mand ...
Page 27
Voltage-Output DACs UPIO Bits (UPSL1, UPSL2, UP0–UP3) The MAX5580–MAX5585 provide two user-programma- ble input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 21. UPIO1 and UPIO2 can be programmed inde- pendently or ...
Page 28
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs UPIO Configuration Table 21 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits. LDAC controls the loading of the DAC registers. ...
Page 29
Voltage-Output DACs t LDL LDAC TOGG PDL t CMS CLR, MID, OR SET OUT_ PDL AFFECTS DAC OUTPUTS (V ) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. OUT_ Figure 5. Asynchronous Signal Timing The SET, MID, ...
Page 30
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs UPIO1 and UPIO2 can each be configured as a gener- al-purpose input (GPI), a general-purpose output low (GPOL general-purpose output high (GPOH). The GPI can serve to detect interrupts from µPs or ...
Page 31
Voltage-Output DACs Applications Information Figure 7 shows the unity-gain MAX5580 in a unipolar output configuration. Table 23 lists the unipolar out- put codes. The MAX5580 outputs can be configured for bipolar operation, as shown in Figure 8. The output ...
Page 32
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Power-Supply and Layout Considerations Bypass the analog and digital power supplies by using a 10µF capacitor in parallel with a 0.1µF capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead ...
Page 33
Voltage-Output DACs TOP VIEW AGND N.C. (*FBB) 3 OUTB 4 MAX5580– N.C. (*FBA) 5 MAX5585 OUTA SCLK 9 **EP DIN 10 TSSOP *FOR THE MAX5581/MAX5583/MAX5585 **EXPOSED PADDLE CONNECTED TO AGND ...
Page 34
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 34 ______________________________________________________________________________________ Package Information PACKAGE OUTLINE, 16, 20, 28, 32, 40L ...
Page 35
Voltage-Output DACs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, Package Information (continued) PACKAGE OUTLINE, 16, 20, 28, 32, 40L ...
Page 36
... Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products Package Information (continued) PACKAGE OUTLINE, TSSOP, 4.40 MM BODY, EXPOSED PAD 21-0108 is a registered trademark of Maxim Integrated Products, Inc ...