max5591 Maxim Integrated Products, Inc., max5591 Datasheet
max5591
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max5591 Summary of contents
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... Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode. The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/ MAX5593 are 10-bit DACs, and the MAX5594/ MAX5595 are 8-bit DACs. The MAX5590/MAX5592/ MAX5594 provide unity-gain-configured output buffers, while the MAX5591/MAX5593/MAX5595 provide force- sense-configured output buffers. The MAX5590– ...
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... MAX5594/MAX5595 (8-bit) Guaranteed monotonic (Note 5590A/M AX 5591A ( 12 eci m al cod 5590B/M AX 5591B ( 12 eci m al cod MAX5592/MAX5593 (10-bit), decimal code = 10 MAX5594/MAX5595 (8-bit), decimal code = 3 MAX5590A/MAX5591A (12-bit) MAX5590B/MAX5590B (12-bit) Full-scale output MAX5592/MAX5593 (10-bit) MAX5594/MAX5595 (8-bit) = +70° ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ (Note 1) PARAMETER SYMBOL Power-Supply Rejection PSRR Ratio REFERENCE ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF (Note 1) PARAMETER SYMBOL ...
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... Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. V OUT (max REF / 2, unless otherwise noted. Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code 1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit). ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) ( 2.7V to 5.25V, GND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL SCLK ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) ( 1.8V to 5.25V, GND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) ( 2.7V to 5.25V, GND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL SCLK ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) ( 1.8V to 5.25V, GND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ( 5V 4.096V 10kΩ REF L INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT B-GRADE -4 0 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit 4.096V REF L DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT) 0.2 0.1 0 -0.1 B-GRADE MIDSCALE -0.2 -40 - TEMPERATURE (°C) SUPPLY CURRENT vs. SUPPLY ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ( 5V 4.096V 10kΩ REF L MAJOR-CARRY TRANSITION GLITCH MAX5590-95 toc19 CS 5V/div OUT_ 2mV/div 250ns/div REFERENCE INPUT BANDWIDTH -10 -15 ...
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... Buffered, Fast-Settling, Octal, 12/10/8-Bit, PIN MAX5590 MAX5591 NAME MAX5592 MAX5593 MAX5594 MAX5595 AGND 3 3 OUTA 4, 8, 17, 21 — N. OUTB 6 7 OUTC 7 10 OUTD SCLK 11 13 DIN DSP DGND 15 17 UPIO1 16 18 UPIO2 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs SERIAL SCLK INTERFACE CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 POWER-DOWN LOGIC LOGIC AND REGISTER DECODE CONTROL PU INPUT REGISTER A INPUT REGISTER H REF 14 ______________________________________________________________________________________ ...
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... UPIO1 UPIO1 AND UPIO2 UPIO2 POWER-DOWN LOGIC LOGIC AND REGISTER DECODE CONTROL PU INPUT REGISTER A INPUT REGISTER H REF ______________________________________________________________________________________ Voltage-Output DACs Functional Diagrams (continued) DV AGND DGND DD MUX DAC REGISTER DACA A DAC DACH REGISTER H MAX5591 MAX5593 MAX5595 DOUT REGISTER FBA OUTA FBH OUTH 15 ...
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... REF where CODE is the numeric value of the DAC’s binary input code and N is the bits of resolution. For the MAX5590/MAX5591 and CODE ranges from 0 to 4095. For the MAX5592/MAX5593 and CODE ranges from 0 to 1023. For the MAX5594/ MAX5595 and CODE ranges from 0 to 255. ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Table 1. Serial Write Data Format MSB CONTROL BITS D11 D10 SCLK DIN CS t CSW DOUTDC1* DOUTDC0 OR DOUTRB* *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Serial-Interface Programming Commands Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5590–MAX5595. Table 2a shows the basic DAC programming com- mands, Table 2b gives the advanced-feature program- ming ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ______________________________________________________________________________________ Voltage-Output DACs 19 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs 20 ______________________________________________________________________________________ ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ______________________________________________________________________________________ Voltage-Output DACs 21 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs IDA_0 IDB_0 IDC_0 IDA_1 IDB_1 IDC_1 IDA_2 IDB_2 IDC_2 IDA_3 IDB_3 IDC_3 IDA_4 IDB_4 IDC_4 IDA_5 IDB_5 IDC_5 IDA_6 IDB_6 IDC_6 IDA_7 IDB_7 IDC_7 IDA_8 IDB_8 IDC_8 IDA_9 IDB_9 IDC_9 IDA_10 IDB_10 IDC_10 IDA_11 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5590–MAX5595 can load all of the input regis- ters ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdown- mode bits determine the output state of the selected channels. The shutdown-control bits put the ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the com- mand in Table ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs UPIO Bits (UPSL1, UPSL2, UP0–UP3) The MAX5590–MAX5595 provide two user-programma- ble input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 22. UPIO1 and UPIO2 can be programmed ...
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... OUTA–OUTH high impedance. Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5590/MAX5592/MAX5594, drive SHDN100K low to pull OUTA–OUTH to AGND with 100kΩ. For the MAX5591/MAX5593/MAX5595, drive low to leave OUTA–OUTH high impedance. Data Read-Back Output Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of Mode 1 Daisy-Chain Data Output ...
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... SHDN1K low to select shutdown mode with OUTA– OUTH internally terminated with 1kΩ to ground, or drive SHDN100K low to select shutdown with an internal 100kΩ termination. For the MAX5591/MAX5593/ MAX5595, drive SHDN1K low for shutdown with 1kΩ output termination, or drive SHDN100K low for shut- down with high-impedance outputs ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, UPIO1 and UPIO2 can each be configured as a gener- al-purpose input (GPI), a general-purpose output low (GPOL general-purpose output high (GPOH). The GPI can serve to detect interrupts from µPs or micro- controllers. ...
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... An example of a custom, fixed gain using the MAX5591’s force-sense output is shown in Figure 9. In this example, the external reference is set to 1.25V, and the gain is set to +1.1V/V with external discrete resis- tors to provide an approximate 0 to 1.375V DAC output voltage range ...
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... Connect AGND and DGND at the low-impedance power-supply sources (Figure 11 ANALOG SUPPLY 10µF 0.1µF 10µ OUTA OUTH FBA MAX5591 MAX5593 MAX5595 AV FBH ONLY DGND** Figure 11. Separate Analog and Digital Power Supplies , DV , and REF DIGITAL SUPPLY AGND ...
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... Pin Configurations 1 28 REF OUTH 4 25 FBH 5 24 FBG MAX5591 6 23 OUTG MAX5593 MAX5595 7 22 OUTF 8 21 FBF 9 20 FBE 10 19 OUTE 11 18 UPIO2 12 17 UPIO1 13 16 DGND TSSOP ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely ...