max5532euat Maxim Integrated Products, Inc., max5532euat Datasheet - Page 14

• Manufacturer Part Number: max5532euat
• Description: Dual, Ultra-low-power, 12-bit, Voltage-output Dacs
• Manufacturer: Maxim Integrated Products, Inc.

The MAX5532–MAX5535 dual, 12-bit, ultra-low-power,
voltage-output DACs offer rail-to-rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 5µA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18µA (max). The MAX5533/MAX5535 include an
internal reference that saves additional board space
and can source up to 8mA, making it functional as a
system reference. The 16MHz, 3-wire serial interface is
compatible with SPI, QSPI, and MICROWIRE protocols.
When V
zero scale with virtually no output glitch. The MAX5532/
MAX5533 output buffers are configured in unity gain
and come in µMAX packages. The MAX5534/MAX5535
output buffers are configured in force sense allowing
users to externally set voltage gains on the output (an
output-amplifier inverting input is available). The
MAX5534/MAX5535 come in 4mm x 4mm thin QFN
packages.
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
14
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DD
is applied, all DAC outputs are driven to
SCLK
DIN
CS
Detailed Description
CONTROL
CONTROL
REGISTER
POWER-
DOWN
LOGIC
SHIFT
AND
REGISTER
REGISTER
INPUT
INPUT
PROGRAMMABLE
V
DD
GND
REFERENCE
2-BIT
REGISTER
REGISTER
DAC
DAC
The MAX5532–MAX5535 use a 3-wire serial interface
that is compatible with SPI/QSPI/MICROWIRE protocols
(Figures 1 and 2).
The MAX5532–MAX5535 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16 bits
are clocked in. The 16 bits consist of 4 control bits
(C3–C0) and 12 data bits (D11–D0) (Table 1). Following
the control bits, the data loads MSB first, D11–D0. The
control bits C3–C0 control the MAX5532–MAX5535, as
outlined in Table 2.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
BUF
REF
Loading the input registers without updating the DAC
registers
Updating the DAC registers from the input registers
Updating all the input and DAC registers simultaneously
Functional Diagrams (continued)
12-BIT DAC
12-BIT DAC
MAX5535
REFOUT
OUTA
FBA
OUTB
FBB
Digital Interface