max5885egmtd Maxim Integrated Products, Inc., max5885egmtd Datasheet - Page 15

• Manufacturer Part Number: max5885egmtd
• Description: Max5885 3.3v, 16-bit, 200msps High Dynamic Performance Dac With Cmos Inputs
• Manufacturer: Maxim Integrated Products, Inc.

harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5885 supports three separate power-supply
inputs for analog (AV
(VCLK) circuitry. Each AV
should at least be decoupled with a separate 0.1µF
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 12). All three
power-supply voltages should also be decoupled at the
point they enter the PC board with tantalum or elec-
trolytic capacitors. Ferrite beads with additional decou-
pling capacitors forming a pi network could also
improve performance.
The analog and digital power-supply inputs AV
VCLK, and DV
age range of 3.3V ±5%.
The MAX5885 is packaged in a 48-pin QFN-EP
(package code: G4877-1), providing greater design
flexibility, increased thermal efficiency**, and optimized
AC performance of the DAC. The EP enables the user
to implement grounding techniques, which are neces-
sary to ensure highest performance operation. The EP
must be soldered down to AGND.
In this package, the data converter die is attached to an
EP lead frame with the back of this frame exposed at the
package bottom surface, facing the PC board side of the
package. This allows a solid attachment of the package
to the PC board with standard infrared (IR) flow soldering
techniques. A specially created land pattern on the PC
board, matching the size of the EP (5mm
ensures the proper attachment and grounding of the
DAC. Designing vias*** into the land area and imple-
menting large ground planes in the PC board design
allow for highest performance operation of the DAC. An
array of at least 3
and 1.2mm pitch between via holes) is recommended for
this 48-pin QFN-EP package.
**Thermal efficiency is not the key factor, since the MAX5885 features low-power operation. The exposed pad is the key element to
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog
ensure a solid ground connection between the DAC and the PC board’s analog ground layer.
ground plane to minimize inductance.
DD
✕
______________________________________________________________________________________
of the MAX5885 allow a supply volt-
3 vias (≤0.3mm diameter per via hole
DD
), digital (DV
DD
Performance DAC with CMOS Inputs
3.3V, 16-Bit, 200Msps High Dynamic
, DV
DD
, and VCLK input
DD
), and clock
✕
5mm),
DD
,
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
The offset error is the difference between the ideal and
the actual offset point. For a DAC, the offset point is the
step value when the digital input is at midscale. This
error affects all codes by the same amount.
Figure 11. 4-Tone MTPR Test Results
Static Performance Parameter Definitions
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
FOUR-TONE MULTITONE POWER RATIO PLOT
0
f
f
T1
T2
26
(f
= 29.9744MHz
= 30.9998MHz
CLK
A
OUT
= 150MHz, f
= -12dB FS
28
Differential Nonlinearity (DNL)
f
T1
30
f
T2
f
f
f
T3
T4
OUT
Integral Nonlinearity (INL)
CENTER
= 32.9773MHz
= 33.8196MHz
32
(MHz)
f
T3
= 31.9885MHz)
34
f
T4
36
Offset Error
38
15