max5883egmtd Maxim Integrated Products, Inc., max5883egmtd Datasheet
max5883egmtd
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max5883egmtd Summary of contents
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Rev 1; 12/03 3.3V, 12-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs General Description The MAX5883 is an advanced, 12-bit, 200Msps digital- to-analog converter (DAC) designed to meet the demanding performance requirements of signal synthe- sis applications found ...
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High Dynamic Performance DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS VCLK to AGND................................-0.3V to +3. VCLK to DGND ...............................-0.3V to +3. ...
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High Dynamic Performance DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference 200Msps unless ...
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High Dynamic Performance DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference 200Msps unless ...
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High Dynamic Performance DAC with CMOS Inputs ( VCLK = 3.3V, external reference SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (f = 50MHz) CLK 100 90 -12dB 0dB FS ...
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High Dynamic Performance DAC with CMOS Inputs ( VCLK = 3.3V, external reference SFDR vs. f AND TEMPERATURE OUT (f = 200MHz -6dB FS 20mA) CLK OUT ...
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High Dynamic Performance DAC with CMOS Inputs PIN NAME 1, 2, 16, N.C. No connection. Do not connect to these pins. Do not tie these pins together. 25–29, 47, 48 XOR Input Pin. XOR = 1 inverts ...
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High Dynamic Performance DAC with CMOS Inputs PIN NAME 38 B6 Data Bit Data Bit Data Bit Data Bit Data Bit Data ...
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High Dynamic Performance DAC with CMOS Inputs Detailed Description The MAX5883 is a high-performance, 12-bit, current- steering DAC (Figure 1) capable of operating with clock speeds up to 200MHz. The converter consists of separate input and DAC ...
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High Dynamic Performance DAC with CMOS Inputs Although not recommended because of additional noise pickup from the ground plane, for single-ended operation IOUTP should be selected as the output, with IOUTN connected to AGND. Note that a ...
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High Dynamic Performance DAC with CMOS Inputs DIGITAL DATA IS LATCHED ON THE RISING EDGE OF CLKP B0 TO B15 SETUP CLKP CLKN IOUT Figure 5. Detailed Timing Relationship Power-Down ...
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High Dynamic Performance DAC with CMOS Inputs AV DD B0–B11 12 AGND Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer AV DV VCLK DD DD IOUTP B0–B11 MAX5883 IOUTN 12 AGND DGND CLKGND Figure ...
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High Dynamic Performance DAC with CMOS Inputs -20 f CLK -30 f CENTER ACLR = 71dB -40 -50 -60 -70 -80 -90 -100 -110 -120 3.5MHz/div Figure 8. ACLR for W-CDMA Modulation, Single Carrier supply decoupling guidelines ...
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High Dynamic Performance DAC with CMOS Inputs Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight line fit (closest approximation to ...
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High Dynamic Performance DAC with CMOS Inputs Adjacent Channel Leakage Power Ratio (ACLR) Commonly used in combination with W-CDMA, ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its ...
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High Dynamic Performance DAC with CMOS Inputs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, (The package drawing(s) in this data sheet may not reflect ...