max5884egmtd Maxim Integrated Products, Inc., max5884egmtd Datasheet
max5884egmtd
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max5884egmtd Summary of contents
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Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs General Description The MAX5884 is an advanced, 14-bit, 200Msps digital- to-analog converter (DAC) designed to meet the demanding performance requirements of signal synthe- sis applications found ...
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High Dynamic Performance DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS VCLK to AGND................................-0.3V to +3. VCLK to DGND ...............................-0.3V to +3. ...
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High Dynamic Performance DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference unless otherwise noted. ≥+25°C guaranteed by production ...
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High Dynamic Performance DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference unless otherwise noted. ≥+25°C guaranteed by production ...
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High Dynamic Performance DAC with CMOS Inputs ( VCLK = 3.3V, external reference SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (f = 50MHz) CLK 100 -12dB -6dB FS ...
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High Dynamic Performance DAC with CMOS Inputs ( VCLK = 3.3V, external reference INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 ...
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High Dynamic Performance DAC with CMOS Inputs PIN NAME 1, 2, 16, N.C. No connection. Do not connect to these pins. Do not tie these pins together. 25–29 XOR Input Pin. XOR = 1 inverts the digital ...
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High Dynamic Performance DAC with CMOS Inputs PIN NAME 38 B8 Data Bit Data Bit Data Bit Data Bit Data Bit Data ...
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High Dynamic Performance DAC with CMOS Inputs Detailed Description The MAX5884 is a high-performance, 14-bit, current- steering DAC (Figure 1) capable of operating with clock speeds up to 200MHz. The converter consists of separate input and DAC ...
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High Dynamic Performance DAC with CMOS Inputs Although not recommended because of additional noise pickup from the ground plane, for single-ended operation IOUTP should be selected as the output, with IOUTN connected to AGND. Note that a ...
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High Dynamic Performance DAC with CMOS Inputs DIGITAL DATA IS LATCHED ON THE RISING EDGE OF CLKP B0 TO B15 SETUP CLKP CLKN IOUT Figure 5. Detailed Timing Relationship Power-Down ...
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High Dynamic Performance DAC with CMOS Inputs AV DD B0–B13 14 AGND Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer AV DV VCLK DD DD IOUTP B0–B13 MAX5884 IOUTN 14 AGND DGND CLKGND Figure ...
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High Dynamic Performance DAC with CMOS Inputs Multitone Testing for GSM/EDGE The transmitter sections of multicarrier base station transceiver systems for GSM/EDGE usually present communication DAC manufacturers with the difficult task of providing devices with higher resolution, ...
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High Dynamic Performance DAC with CMOS Inputs Table 2. GSM/EDGE Noise Requirements for Multicarrier Systems CARRIER DAC NOISE DENSITY NUMBER OF POWER LEVEL CARRIERS (dB FS -12 Other key factors in selecting the appropriate ...
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High Dynamic Performance DAC with CMOS Inputs harmonic distortion components and optimize the DAC’s dynamic performance. Digital signal paths should be kept short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5884 ...
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High Dynamic Performance DAC with CMOS Inputs A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of ...
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High Dynamic Performance DAC with CMOS Inputs Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier fre- quency (maximum signal components) to the RMS value of their next-largest distortion component. SFDR is ...
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High Dynamic Performance DAC with CMOS Inputs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, (The package drawing(s) in this data sheet may not reflect ...