max5886 Maxim Integrated Products, Inc., max5886 Datasheet
max5886
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max5886 Summary of contents
Page 1
... The digital and clock inputs of the MAX5886 are designed for differential low-voltage differential signal (LVDS)-compatible voltage levels. The MAX5886 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40° ...
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High Dynamic Performance DAC with Differential LVDS Inputs ABSOLUTE MAXIMUM RATINGS VCLK to AGND................................-0.3V to +3. VCLK to DGND ...............................-0.3V to +3. ...
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High Dynamic Performance DAC with Differential LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference analog output, 50Ω double terminated (Figure 7), ...
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High Dynamic Performance DAC with Differential LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference analog output, 50Ω double terminated (Figure 7), ...
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... Power-Supply Rejection Ratio Note 1: Nominal full-scale current I OUT Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5886. Note 3: Parameter measured single ended into a 50Ω termination resistor. Note 4: Parameter guaranteed by design. Note 5: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance. ...
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High Dynamic Performance DAC with Differential LVDS Inputs ( VCLK = 3.3V, external reference SFDR vs. OUTPUT FREQUENCY (f = 300MHz -6dB FS) CLK OUT 100 I = 20mA ...
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High Dynamic Performance DAC with Differential LVDS Inputs PIN NAME 1–8, 23, 34, N.C. Not connected. Do not connect to these pins. Do not tie these pins together. 35–38 9, 41, 60, 62 DGND Digital Ground Digital ...
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... Pin Description (continued) FUNCTION limited output drive capability REFIO must be buffered with an external amplifier, if heavier loading is required. Architecture The MAX5886’s reference circuit (Figure 2) employs a control amplifier, designed to regulate the full-scale current I OUT DAC. Configured as a voltage-to-current amplifier, the output current can be calculated as follows: ...
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... High Dynamic Performance DAC with Differential LVDS Inputs DV DGND DD 1.2V REFERENCE REFIO FSADJ CLKN CLKP Figure 1. Simplified MAX5886 Block Diagram Table 1. I and R Selection Matrix Based on a Typical 1.200V Reference Voltage OUT SET FULL-SCALE CURRENT REFERENCE CURRENT I (mA) OUT ...
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... AC-coupled ECL drive for best performance. Data Timing Relationship Figure 5 shows the timing relationship between differ- ential, digital LVDS data, clock, and output signals. The MAX5886 features a 1.8ns hold, a -0.8ns setup, and a 1.8ns propagation delay time. There is a 3.5 clock- 10 ______________________________________________________________________________________ AV ...
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... A single pin (PD) is used to control the power-down mode ( reactivate the DAC ( after power-down. Enabling the power-down mode of the MAX5886 allows the overall power consumption to be reduced to less than 1mW. The MAX5886 requires 10ms to wake up from power-down and enter a fully operational state. ______________________________________________________________________________________ ...
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... The distortion performance of the DAC depends on the load impedance. The MAX5886 is optimized for a 50Ω double termination. It can be used with a transformer output as shown in Figure 7 or just one 50Ω resistor from each output to ground and one 50Ω resistor between the outputs ...
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... CLK applied to the MAX5886 (including measurement sys- tem limitations*). Figure 10 illustrates the ACLR test results for the MAX5886 with a four-carrier W-CDMA signal at an out- put frequency of 63.98MHz and sampling frequency of 184.32MHz. Considerable care must be taken to ensure accurate measurement of this parameter. Multitone Testing for GSM/EDGE ...
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... FS. Under these conditions, the DAC yields an MTPR performance of -78dBc. Grounding, Bypassing, and Power-Supply Grounding and power-supply decoupling can strongly influence the performance of the MAX5886. Unwanted digital crosstalk may couple through the input, refer- ence, power supply, and ground connections, affecting dynamic performance. Proper grounding and power- ...
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... MAX5886 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PC board’s analog ground layer. ...
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... It is important to connect as many vias as possible to the analog ground plane to minimize inductance. BYPASSING—DAC LEVEL AV VCLK DD 0.1µF AGND CLKGND B0–B11 MAX5886 12 0.1µF DGND DV DD Figure 13. Recommended Power-Supply Decoupling and Bypassing Circuitry 16 ______________________________________________________________________________________ Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB ...
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... IMDs. The two-tone IMD performance of the MAX5886 was tested with the two individual input tone levels set to at least -6dB FS and the four-tone perfor- mance was tested according to the GSM model at an output frequency of 32MHz and amplitude of -12dB FS ...
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... MAX5886 Package Code: G6800-4 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...