max5858a Maxim Integrated Products, Inc., max5858a Datasheet
max5858a
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max5858a Summary of contents
Page 1
... DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5858A to be updated on a single 10-bit bus. The MAX5858A features digital control of channel gain matching to within ± ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ABSOLUTE MAXIMUM RATINGS AGND, DGND, PGND ..........-0. DA9–DA0, DB9–DB0, CW, REN, PLLF, PLLEN to AGND, DGND, PGND........................................................-0.3V to +4V ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x ELECTRICAL CHARACTERISTICS (continued) ( 3V, AGND = DGND = PGND = 1.2V 20mA, output amplitude = 0dB FS, differential output, ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ELECTRICAL CHARACTERISTICS (continued) ( 3V, AGND = DGND = PGND = 1.2V 20mA, output amplitude = ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x ELECTRICAL CHARACTERISTICS (continued) ( 3V, AGND = DGND = PGND = 1.2V 20mA, output amplitude = 0dB FS, differential output, ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ELECTRICAL CHARACTERISTICS (continued) ( 3V, AGND = DGND = PGND = 1.2V 20mA, output amplitude = ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x ( 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled differential output +25°C, unless otherwise noted.) ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ( 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled differential output ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x ( 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled differential output +25°C, unless otherwise noted.) ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ( 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled differential output ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x ( 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled differential output +25°C, unless otherwise noted.) ...
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... Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0 11 DA1 Channel A Input Data Bit 1 12 DA0 Channel A Input Data Bit 0 (LSB) 12 ______________________________________________________________________________________ Typical Operating Characteristics (continued) DYNAMIC RESPONSE FALL TIME 200mV/div R = 50Ω L SINGLE ENDED FUNCTION = 20mA, FS MAX5858A toc34 200mV/div 10ns/div Pin Description ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x PIN NAME 13 DB9 Channel B Input Data Bit 9 (MSB) 14 DB8 Channel B Input Data Bit 8 15 DB7 Channel B Input Data Bit 7 16 DB6 Channel B Input Data Bit ...
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... The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control. The MAX5858A accepts an input data rate 165MHz or a DAC conversion rate 300MHz. The inputs are latched on the rising edge of the clock where- as the output latches on the following rising edge. ...
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... Interpolation Filters and PLL The programmable interpolation filters multiply the MAX5858A input data rate by a factor of two or four to separate the reconstructed waveform spectrum and the first image. The original spectral images, appearing around multiples of the DAC input data rate, are attenu- ated at least 60dB by the internal digital filters ...
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... Filter gain/phase match FS ANALOG OUT MAINTAINED OVER ENTIRE SUPPLY RANGE 2.7V TO 3.3V 10 CHA AOUT DAC 10 CHB BOUT DAC DIV-4 DIV-2 DIV-1 MAX5858A DISADVANTAGE • High order filter • Filter gain/phase match • High clock rate • High data rate • None ...
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... This example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing sys- tem complexity, improving dynamic performance and lowering cost. Data can be written to the MAX5858A at much lower speeds while achieving image attenuation greater than 60dB and image separation beyond three octaves ...
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... and I REFO SET is the reference resistor that determines the amplifier out- put current of the MAX5858A (Figure 4). This current is mirrored into the current-source array where I distributed between matched current segments and summed to valid output current readings for the DACs. REN 1.24V ...
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... Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x External Reference To disable the internal reference of the MAX5858A, con- nect REN Apply a temperature-stable, external DD reference to REFO to set the full-scale output (Figure 5). For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference ...
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... Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL Figure 6 depicts the write cycle of the MAX5858A in 4x interpolation mode. With the interpolation feature enabled, the device can operate with the PLL enabled or disabled. With the PLL disabled (PLLEN = 0), the clock signal is applied to CLKXP/CLKXN and internally divided generate the DAC’ ...
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... CLK IS AN OUTPUT WHEN PLL IS DISABLED WITH PLLEN CONNECTED TO GND, OTHERWISE INPUT. Figure 7. Timing Diagram for Interleave Data Mode (IDE = High) The MAX5858A can operate in interleave data mode by setting IDE = 1. In interleave data mode, data for both DAC channels is written through input port A. Channel ...
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... Analog quadrature upconverters have a DC common-mode input require- ment of typically 0.7V to 1.0V. The MAX5858A differential I/Q outputs can maintain the desired full-scale original level at the required 0.7V to 1.0V DC common-mode volt- age when powered from a single 2.85V (±5%) supply. ...
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... Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x The MAX5858A is packaged in a 48-pin TQFP-EP pack- age, providing design flexibility, increased thermal effi- ciency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. In this package, the data converter die is attached to ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of ...
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Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, (The package drawing(s) in this data sheet may not reflect the most current specifications. ...