max5851 Maxim Integrated Products, Inc., max5851 Datasheet - Page 10

• Manufacturer Part Number: max5851
• Description: Max5851 Dual, 8-bit, 80msps, Current-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

Dual, 8-Bit, 80Msps, Current-Output DAC
10
21, 22
27, 30
9, 10,
PIN
11
12
13
14
15
16
17
18
19
20
23
24
25
26
28
29
31
______________________________________________________________________________________
1
2
3
4
5
6
7
8
DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control
DA4/REN
DA5/IDE
DA7/PD
DA3/G3
DA2/G2
DA1/G1
DA0/G0
CLKXN
CLKXP
NAME
DGND
CGND
DV
CV
REFO
N.C.
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DCE
CLK
CW
DD
DD
Channel A Input Data Bit 7 (MSB)/Power-Down
Channel A Input Data Bit 5/Interleaved Data Enable
Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2
Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1
Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0
No Connection. Do not connect to these pins.
Channel B Input Data Bit 7 (MSB)
Channel B Input Data Bit 6
Channel B Input Data Bit 5
Channel B Input Data Bit 4
Channel B Input Data Bit 3
D i g i tal P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.
Digital Ground
Channel B Input Data Bit 2
Channel B Input Data Bit 1
Channel B Input Data Bit 0 (LSB)
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
Active-Low Differential Clock Enable Input. Drive DCE low to enable differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CV
C l ock P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a
single-ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-
ended output that mirrors differential clock inputs CLKXP and CLKXN. See the Clock Modes section for
more information on CLK.
Clock Ground
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor.
FUNCTION
DD
when the differential clock is disabled.
Pin Description