max5893egk-d Maxim Integrated Products, Inc., max5893egk-d Datasheet
max5893egk-d
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max5893egk-d Summary of contents
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... Selectable Modulator LO Frequency: OFF Selectable Output Filter: Lowpass or Highpass Channel Gain and Offset Adjustment ♦ EV Kit Available (Order the MAX5893EVKIT) PART / MAX5893EGK-D MAX5893EGK Dry pack. *EP = Exposed paddle. +Denotes lead-free package. PART MAX5893 Applications MAX5894 MAX5895 MAX5898 DATA ...
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Interpolating and Modulating Dual DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS GND, DACREF ..................-0.3V to +2.16V DD1.8 DD1 GND, DACREF ........-0.3V to +3.9V DD3.3 CLK DD3.3 DATACLK, A0–A11, ...
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Interpolating and Modulating ELECTRICAL CHARACTERISTICS (continued) ( 1.8V DD1.8 DD1.8 CLK mode, 50Ω double-terminated outputs, external reference at 1.25V +25°C, unless otherwise noted.) (Note 2) A PARAMETER SYMBOL ...
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Interpolating and Modulating Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( 1.8V DD1.8 DD1.8 CLK mode, 50Ω double-terminated outputs, external reference at 1.25V +25°C, unless otherwise noted.) ...
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Interpolating and Modulating ELECTRICAL CHARACTERISTICS (continued) ( 1.8V DD1.8 DD1.8 CLK mode, 50Ω double-terminated outputs, external reference at 1.25V +25°C, unless otherwise noted.) (Note 2) A PARAMETER SYMBOL ...
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Interpolating and Modulating Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( 1.8V DD1.8 DD1.8 CLK mode, 50Ω double-terminated outputs, external reference at 1.25V +25°C, unless otherwise noted.) ...
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Interpolating and Modulating ( 1.8V DD1.8 DD1.8 CLK 50Ω load +25°C, unless otherwise noted.) A IN-BAND SFDR vs. OUTPUT FREQUENCY f = 125MWps, 2x INTERPOLATION DATA 120 -0.1dBFS -6dBFS 100 ...
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Interpolating and Modulating Dual DAC with CMOS Inputs ( 1.8V DD1.8 DD1.8 CLK 50Ω load +25°C, unless otherwise noted.) A GAIN MISMATCH vs. TEMPERATURE f = 125Msps, 2x INTERPOLATION DATA ...
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Interpolating and Modulating ( 1.8V DD1.8 DD1.8 CLK 50Ω load +25°C, unless otherwise noted.) A WCDMA ACLR vs. OUTPUT FREQUENCY f = 122.88MWps, 4x INTERPOLATION DATA 100 90 SINGLE-CARRIER ALTERNATE ...
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Interpolating and Modulating Dual DAC with CMOS Inputs PIN NAME 1 CLKP Noninverting Differential Clock Input 2 CLKN Inverting Differential Clock Input 22–25, N.C. Internally Connected. Do not connect. 40–43 Digital Power Supply. Accepts a ...
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Interpolating and Modulating PIN NAME Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with 53 DD1.8 a 0.1µF capacitor as close to the pin as possible. 54, 56, ...
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Interpolating and Modulating Dual DAC with CMOS Inputs Detailed Description The MAX5893 dual, 500Msps, high-speed, 12-bit, cur- rent-output DAC provides superior performance in communication systems requiring low-distortion ana- log-signal reconstruction. The MAX5893 combines two DAC cores with 8x/4x/2x/1x ...
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Interpolating and Modulating When writing to the MAX5893, data is shifted into SDI; data is shifted out of SDO in a read operation. Bits the control byte are the address bits. These bits set ...
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Interpolating and Modulating Dual DAC with CMOS Inputs CS SCLK SDI SDO Figure 3. SPI Serial-Interface Timing Diagram 14 ______________________________________________________________________________________ SDS SDH t SDV ...
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Interpolating and Modulating Programming Registers Programming its registers with the SPI serial interface sets the MAX5893 operation modes. Table 2 shows all Table 2. MAX5893 Programmable Registers ADD BIT 7 BIT 6 Software Reset 0 = MSB first ...
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Interpolating and Modulating Dual DAC with CMOS Inputs Address 00h Bit 6 Logic 0 (default) causes the serial port to use MSB first address/data format. When set to a logic 1, the serial port will use LSB first ...
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Interpolating and Modulating Address 07h Bit 7 Logic 0 (default) adds the 10 bits offset cur- rent to OUTIN. A logic 1 adds the 10 bits off- set current to OUTIP. Address 08h Bits 7–0 These 8 bits ...
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Interpolating and Modulating Dual DAC with CMOS Inputs tionship and detects if the phase drifts more than ±1 data clock cycle. If this occurs, the synchronizer auto- matically reestablishes synchronization. However, dur- ing the resynchronization phase ...
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Interpolating and Modulating Interpolating Filter The MAX5893 features three cascaded FIR half-band filters. The interpolating filters are enabled or disabled in combinations to support 1x (no interpolation), 2x, 4x interpolation. Bits 7 and 6 of register ...
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Interpolating and Modulating Dual DAC with CMOS Inputs The programmable interpolation filters multiply the MAX5893 input data rate by a factor of 2x, 4x separate the reconstructed waveform spectrum and the DAC image. The original ...
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Interpolating and Modulating images at odd numbers of f are filtered. At the output of S the first filter, the images are then passed to the second interpolating filter, which is similar to ...
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Interpolating and Modulating Dual DAC with CMOS Inputs SIGNAL IMAGE INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL OUTPUT SPECTRUM OF THE FIRST FILTER INPUT SIGNAL SPECTRUM AND SECOND FILTER RESPONSE f 2f ...
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Interpolating and Modulating SIGNAL IMAGE INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL OUTPUT SPECTRUM OF THE FIRST FILTER INPUT SIGNAL SPECTRUM AND SECOND FILTER RESPONSE SIGNAL OUTPUT SPECTRUM OF ...
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Interpolating and Modulating Dual DAC with CMOS Inputs Digital Modulator The MAX5893 features digital modulation at frequen- cies and where the input to the modulator. f equals f ...
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Interpolating and Modulating Power-Down Mode The MAX5893 features three power-saving modes. Each DAC can be individually powered down through bits 2 and 3 of address 00h. The interpolation filters can also be powered down through bit 4 of ...
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Interpolating and Modulating Dual DAC with CMOS Inputs sources directly to the device without external resistors to define the DC level. The input resistance of CLKP and CLKN is 5kΩ. A convenient way to apply a differential signal ...
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Interpolating and Modulating amplitudes recommended to connect the trans- former center tap to ground transformer is not used, the outputs must have a resistive termination to ground. Figure 17 shows the MAX5893 output configured ...
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Interpolating and Modulating Dual DAC with CMOS Inputs For stable operation with the internal reference, REFIO should be decoupled to GND with a 1µF capacitor. REFIO must be buffered with an external amplifier, if heavy loading is required, ...
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Interpolating and Modulating Power Supplies, Bypassing, Decoupling, and Layout Grounding and power-supply decoupling strongly influ- ence the MAX5893 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications like ...
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Interpolating and Modulating Dual DAC with CMOS Inputs However, noise sources such as thermal noise, refer- ence noise, clock jitter, etc. affect the ideal reading. Therefore, SNR is computed by taking the ratio of the RMS signal to ...
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Interpolating and Modulating TOP VIEW 68 67 EXPOSED PADDLE CLKP 1 CLKN 2 N.C. 3 N. VDD1.8 A11 7 A10 VDD3.3 DATACLK ...
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Interpolating and Modulating Dual DAC with CMOS Inputs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) 32 ______________________________________________________________________________________ Package Information PACKAGE OUTLINE, 68L ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2007 Maxim Integrated Products Dual DAC with CMOS Inputs Package Information (continued) PACKAGE OUTLINE, 68L QFN, 10x10x0 registered trademark of Maxim Integrated Products, Inc 21-0122 2 ...