max5812peut-t Maxim Integrated Products, Inc., max5812peut-t Datasheet - Page 8

• Manufacturer Part Number: max5812peut-t
• Description: Max5812 12-bit Low-power, 2-wire, Serial Voltage-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Figure 1. Two-Wire Serial lnterface Timing Diagram
and a serial clock line (SCL). The MAX5812 is SMBus
compatible within the range of V
and SCL facilitate bidirectional communication between
the MAX5812 and the master at rates up to 400kHz.
Figure 1 shows the 2-wire interface timing diagram. The
MAX5812 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter, typically a microcontroller, initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5812 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (S
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5812 SDA and SCL drivers are open-drain out-
puts, requiring a pullup resistor (500Ω or greater) to
generate a logic high voltage (see the Typical Operating
Circuit). Series resistors R
resistors protect the input stages of the MAX5812 from
high-voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while the SCL is high are control signals (see the
START and STOP Conditions section). SDA and SCL
idle high when the I
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
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SDA
SCL
t
HD, STA
START CONDITION
2
C bus is not busy.
t
LOW
START and STOP Conditions
t
S
R
t
are optional. These series
t
SU, DAT
HIGH
DD
t F
= 2.7V to 3.6V. SDA
t
HD, DAT
r
) condition and
Bit Transfer
REPEATED START CONDITION
t
SU, STA
Figure 2. START/STOP Conditions
Figure 3. Early STOP condition
SDA
SCL
t
HD, STA
SCL
SDA
SCL
SDA
S
ILLEGAL EARLY STOP CONDITION
START
STOP
LEGAL STOP CONDITION
t
SP
Sr
START
ILLEGAL
STOP
t
SU, STO
CONDITION
STOP
t
BUF
CONDITION
P
START