max5811peut-t Maxim Integrated Products, Inc., max5811peut-t Datasheet - Page 8

• Manufacturer Part Number: max5811peut-t
• Description: Max5811 10-bit, Low-power, 2-wire Interface, Serial, Voltage-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Figure 1. 2-Wire Serial lnterface Timing Diagram
a serial clock line (SCL). The MAX5811 is SMBus com-
patible within the range of V
SCL facilitate bidirectional communication between the
MAX5811 and the master at rates up to 400kHz.
1
MAX5811 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5811 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (S
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5811 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor (500Ω or greater) to
generate a logic high voltage (see Typical Operating
Circuit). Series resistors R
resistors protect the input stages of the MAX5811 from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions). SDA and SCL idle high when the
I
8
2
C bus is not busy.
shows the 2-wire interface timing diagram. The
SDA
SCL
t
_______________________________________________________________________________________
HD, STA
START CONDITION
t
LOW
t
R
S
t
t
SU, DAT
HIGH
DD
are optional. These series
= 2.7V to 3.6V. SDA and
t
F
t
HD, DAT
r
) condition and
Bit Transfer
Figure
REPEATED START CONDITION
t
SU, STA
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
Figure 2. START/STOP Conditions
Figure 3. Early STOP Condition
t
HD, STA
SDA
SCL
SCL
SDA
SCL
SDA
S
ILLEGAL EARLY STOP CONDITION
START
STOP
LEGAL STOP CONDITION
t
SP
START and STOP Conditions
START
ILLEGAL
t
SU, STO
S
STOP
r
CONDITION
STOP
t
BUF
CONDITION
START
P