max5864 Maxim Integrated Products, Inc., max5864 Datasheet
max5864
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max5864 Summary of contents
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... The MAX5864 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5864 operates on a +2.7V to +3.3V ana- log power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 5.6mA in idle mode and 1µA in shutdown mode. The MAX5864 is specified for the extended (-40° ...
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Ultra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND OGND................................-0.3V to +3. GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ...
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Performance, 22Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Performance, 22Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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... A guaranteed by design and characterization. Note 2: The minimum clock frequency for the MAX5864 is 7.5MHz. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. ...
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Ultra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
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Performance, 22Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
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Ultra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
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Performance, 22Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
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Ultra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End PIN NAME 1 REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass 0.1µF capacitor. ...
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... DAC can be shared to reduce the digital I single 10-bit parallel multiplexed bus. In FDD mode, the full-scale signals. P-P MAX5864 digital I/O can be configured for an 18-bit, parallel multiplexed bus to match the dual 8-bit ADC and dual 10-bit DAC. The MAX5864 features an internal precision 1.024V bandgap reference is stable over the entire power-supply and temperature ranges ...
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... MAX5864 and degrading its dynamic performance. Buffers on the digital outputs isolate them from heavy capacitive loads. Adding 100Ω resistors in series with the digital outputs close to the MAX5864 helps improve ADC performance. Refer to the MAX5865 EV kit schematic for an example of the digital outputs driving a digital buffer through 100Ω ...
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... This simplifies the analog interface between RF quadrature upconverters and the MAX5864. RF upconverters require a 1.3V to 1.5V com- mon-mode bias. The internal DC common-mode bias eliminates discrete level setting resistors and code-gen- erated level-shifting while preserving the full dynamic ...
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... N-1 DAC Timing The 3-wire serial interface controls the MAX5864 opera- tion modes. Upon power-up, the MAX5864 must be programmed to operate in the desired mode. Use the 3-wire serial interface to program the device for the shut- down, idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data register sets the operation modes as shown in The serial interface remains active in all six modes ...
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... Don’t care. Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX5864 and placing the ADCs’ digital outputs in tri-state mode. When the ADCs’ outputs transition from tri-state to on, the last converted word is placed on the digital outputs. ...
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... SINAD performance and DAC settling to 10 LSB error times are measured after the 8-bit WAKE ENABLE serial command is latched into the MAX5864 by CS transition high. t for Xcvr mode is dominated by ENABLE the DAC wake-up time. The recovery time is 10µs to switch between Xcvr, Tx modes. The recovery time is 40µ ...
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... Connecting the center tap of the transformer to COM provides a V former can be used step-up transformer can be selected to reduce the drive requirements. In general, the MAX5864 provides better SFDR and THD with fully differential input signals than single-ended signals, (Table 4). especially for high-input frequencies. In differential mode, even-order harmonics are lower as both inputs ...
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... C IN 22pF Figure 9. Single-Ended Drive for ADCs 20 ______________________________________________________________________________________ Drive the MAX5864 ADCs with op amps when a balun V OUT transformer is not available. ADCs being driven by op amps for AC-coupled single- ended, and DC-coupled differential applications. Amplifiers such as the MAX4354/MAX4454 provide high speed, high bandwidth, low noise, and low distor- tion to maintain the input signal integrity ...
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... R8 R9 600Ω 600Ω R10 R11 600Ω 600Ω ADC MAX2391 QUADRATURE DEMODULATOR ADC DAC MAX2395 QUADRATURE TRANSMITTER DAC MAX5864 MAX5864 R ISO 22Ω INA 5pF COM R ISO 22Ω INA 5pF CLK ADC OUTPUT MUX CLK ...
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... Connect the MAX5864 exposed backside paddle to the GND plane. Join the two ground planes at a single point such that the noisy digital ground currents do not inter- fere with the analog ground plane ...
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Performance, 22Msps Analog Front End Dynamic Parameter Definitions ADC and DAC Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either ...
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... Total Harmonic Distortion ... + V ) = 20log V 1 through 2 Spurious-Free Dynamic Range Pin Configuration SCLK 34 DIN DD9 31 DD8 MAX5864 30 DD7 DD6 29 28 DD5 27 DD4 DD3 26 25 DD2 QFN Chip Information ...
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Performance, 22Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) D D/2 ______________________________________________________________________________________ Ultra-Low-Power, High Dynamic- k E/2 (NE- ...
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Ultra-Low-Power, High-Dynamic- Performance, 22Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) COMMON DIMENSIONS Maxim cannot assume responsibility for use of any ...