adc14v155lfeb National Semiconductor Corporation, adc14v155lfeb Datasheet

no-image

adc14v155lfeb

Manufacturer Part Number
adc14v155lfeb
Description
14-bit, 155 Msps, 1.1 Ghz Bandwidth A/d Converter With Lvds Outputs
Manufacturer
National Semiconductor Corporation
Datasheet
© 2007 National Semiconductor Corporation
ADC14V155
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with
LVDS Outputs
General Description
The ADC14V155 is a high-performance CMOS analog-to-
digital converter with LVDS outputs. It is capable of converting
analog input signals into 14-Bit digital words at rates up to 155
Mega Samples Per Second (MSPS). Data leaves the chip in
a DDR (Dual Data rate) format; this allows both edges of the
output clock to be utilized while achieving a smaller package
size. This converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize power consumption and the external com-
ponent count, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
bandwidth of 1.1 GHz. The ADC14V155 operates from dual
+3.3V and +1.8V power supplies and consumes 951 mW of
power at 155 MSPS.
The separate +1.8V supply for the digital output interface al-
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 15 mW while
still allowing fast wake-up time to full operation. In addition
there is a sleep feature which consumes 50 mW of power and
has a faster wake-up time.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14V155 can
be operated with an external reference.
Clock mode (differential versus single-ended) and output data
format (offset binary versus 2's complement) are pin-se-
lectable. A duty cycle stabilizer maintains performance over
a wide range of input clock duty cycles.
The ADC14V155 is pin-compatible with the ADC12V170. It is
available in a 48-lead LLP package and operates over the
industrial temperature range of −40°C to +85°C.
Block Diagram
300052
Features
Key Specifications
Applications
1.1 GHz Full Power Bandwidth
Internal sample-and-hold circuit
Low power consumption
Internal precision 1.0V reference
Single-ended or Differential clock modes
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V supply operation
Power-down and Sleep modes
Offset binary or 2's complement output data format
Dual Data Rate (DDR) LVDS outputs
Pin-compatible: ADC12V170
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
Resolution
Conversion Rate
SNR (f
SFDR (f
ENOB (f
Full Power Bandwidth
Power Consumption
High IF Sampling Receivers
Wireless Base Station Receivers
Power Amplifier Linearization
Multi-carrier, Multi-mode Receivers
Test and Measurement Equipment
Communications Instrumentation
Radar Systems
IN
IN
IN
= 70 MHz)
= 70 MHz)
= 70 MHz)
30005202
71.7 dBFS (typ)
86.9 dBFS (typ)
www.national.com
October 2007
11.5 bits (typ)
951 mW (typ)
1.1 GHz (typ)
155 MSPS
14 Bits

Related parts for adc14v155lfeb

adc14v155lfeb Summary of contents

Page 1

... The ADC14V155 is pin-compatible with the ADC12V170 available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Block Diagram © 2007 National Semiconductor Corporation Features ■ 1.1 GHz Full Power Bandwidth ■ ...

Page 2

... Connection Diagram Ordering Information Industrial (−40°C www.national.com ≤ ≤ T +85°C) A ADC14V155CISQ ADC14V155LFEB Evaluation Board (f ADC14V155HFEB Evaluation Board (f 2 30005201 Package 48 Pin LLP <150 MHz) IN >150 MHz) IN ...

Page 3

Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I − REF 8 CLK_SEL/DF 7 PD/Sleep Equivalent Circuit Differential analog input pins. ...

Page 4

Pin No. Symbol 11 CLK+ 12 CLK− DIGITAL I/O 17 D1-/D0- 18 D1+/D0+ 19 D3-/D2- 20 D3+/D2+ 21 D5-/D4- 22 D5+/D4+ 23 D7-/D6- 24 D7+/D6+ 27 D9-/D8- 28 D9+/D8+ 29 D11-/D10- 30 D11+/D10+ 31 D13-/D12- 32 D13+/D12+ 15 OVR- 16 ...

Page 5

Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Voltage ( –V | ...

Page 6

Converter Electrical Characteristics Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF Typical values are for T = 25°C. Boldface limits apply for T A Symbol Parameter STATIC CONVERTER CHARACTERISTICS Resolution ...

Page 7

Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF Typical values are for T = 25°C. Boldface limits apply for T A Symbol Parameter DYNAMIC CONVERTER CHARACTERISTICS, ...

Page 8

Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF Typical values are for T = 25°C. Boldface limits apply for T A Symbol Parameter CLK ...

Page 9

Timing and AC Characteristics Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF Typical values are for T = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface ...

Page 10

Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

Page 11

Timing Diagram Output Timing 11 30005220 www.national.com ...

Page 12

Transfer Characteristic FIGURE 1. Transfer Characteristic (Offset Binary Format) Typical Performance Characteristics, DNL, INL Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF Typical values are for T = 25°C. (Notes ...

Page 13

Typical Performance Characteristics, Dynamic Performance Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF CLK Binary Format. Typical values are for T A SNR, SINAD, SFDR vs. f SNR, SINAD, SFDR ...

Page 14

Typical Performance Characteristics, Dynamic Performance Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF Binary Format. Typical values are for T SNR, SINAD, SFDR vs. V SNR, SINAD, SFDR vs. Temperature ...

Page 15

Typical Performance Characteristics, Dynamic Performance Unless otherwise specified, the following specifications apply +1.8V, Internal V = +1.0V REF CLK Binary Format. Typical values are for T A Spectral Response @ 70 MHz Input Spectral Response ...

Page 16

Functional Description Operating on dual +3.3V and +1.8V supplies, the AD- C14V155 digitizes a differential analog input signal to 14 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The ...

Page 17

− V − REF CM REF V − REF CM REF − ...

Page 18

Control Inputs 2.3.1 Power-Down & Sleep (PD/Sleep) The power-down and sleep modes can be enabled through this three-state input pin. Table 2 shows how to utilize these options. TABLE 2. Power Down/Sleep Selection Table PD Input Voltage Power State ...

Page 19

PCB traces less than 2 inches long; longer traces are more susceptible to noise. Try to place the FIGURE 4. Application Circuit using Transformer Drive Circuit 5.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be ...

Page 20

All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The ADC14V155 should be be- tween these two areas. Furthermore, all components in the reference circuitry and the input signal chain that are ...

Page 21

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead LLP Package Ordering Number ADC14V155CISQ NS Package Number SQA48A 21 www.national.com ...

Page 22

... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

Related keywords