adv7174 Analog Devices, Inc., adv7174 Datasheet - Page 37

• Manufacturer Part Number: adv7174
• Description: Chip Scale Pal/ntsc Video Encoder With Advanced Power Management
• Manufacturer: Analog Devices, Inc.

TELETEXT REQUEST CONTROL REGISTER (TC07)
Bits:
Address:
Teletext control register is an 8-bit-wide register (see Figure 50).
Table 17. Teletext Request Control Register
Bit Name
TTXREQ Rising Edge Control
TTXREQ Falling Edge Control
CGMS_WSS REGISTER 0 (C/W0)
Bits:
Address:
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register.
Table 18. C/W0 Bit Description
Bit Name
CGMS Data Bits
CGMS CRC Check Con
CGMS Odd Field Control
CGMS Even Field Control
WSS Control
TC07–TC00
SR4–SR0 = 19H
C/W07–C/W00
SR4–SR0 = 16H
t
rol
C/W07
SIGNAL CONTROL
WIDE SCREEN
0
1
Bit No.
C/W03–C/W00
C/W04
C/W05
C/W06
C/W07
C/W07
TC07
TC07 TC06 TC05 TC04
DISABLE
ENABLE
0
0
"
1
1
TTXREQ RISING EDGE CONTROL
Bit No.
TC07–TC04
TC03–TC00
C/W06
CGMS EVEN FIELD
0
1
0
0
"
1
1
CONTROL
TC06
C/W06
ENABLE
DISABLE
0
0
"
1
1
C/W05
CGMS ODD FIELD
Description
These four data bits are the final four bits of the CGMS data output stream. Note it is
CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.
When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check
sequence, are calculated internally by the ADV7174/ADV7179. If this bit is disabled (0), the
CRC values in the register are output to the CGMS data stream.
When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode.
When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode.
When this bit is set (1), wide screen signaling is enabled. Note this is only valid in PAL mode.
0
1
0
1
"
0
1
CONTROL
TC05
C/W05
DISABLE
ENABLE
Figure 50. Teletext Control Register
Figure 51. CGMS_WSS Register 0
Description
These bits control the position of the rising edge of TTXREQ. It can be
programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see
Figure 50).
These bits control the position of the falling edge of TTXREQ. It can be
programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls
the active window for Teletext data. Increasing this value reduces the amount of
Teletext bits below the default of 360. If Bits TC03–TC00 are 00H when Bits TC07–
TC04 are changed, the falling edge of TTXREQ tracks that of the rising edge, i.e.,
the time between the falling and rising edge remains constant (see Figure 49).
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
C/W04
CGMS CRC CHECK
0
1
Rev. A | Page 37 of 52
CONTROL
TC04
C/W04
DISABLE
ENABLE
TC03
TC03 TC02 TC01 TC00
C/W03
0
0
"
1
1
TTXREQ FALLING EDGE CONTROL
0
0
"
1
1
TC02
C/W02
CGMS DATA BITS
0
0
"
1
1
C/W03 – C/W00
0
1
"
0
1
TC01
C/W01
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TC00
C/W00
ADV7174/ADV7179