adv7533 Analog Devices, Inc., adv7533 Datasheet - Page 9

• Manufacturer Part Number: adv7533
• Description: Mipi/dsi Receiver With Hdmi Transmitter
• Manufacturer: Analog Devices, Inc.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
F6, G6
F5, G5
F4, G4
F3, G3
F2, G2
C3
C5
C4
C1
C2
D3
B7, A7
A2, A1
A4, A3
A6, A5
D5
B4
D4, E3
Mnemonic
DRx3−/DRx3+
DRx2−/DRx2+
DRx1−/DRx1+
DRx0−/DRx0+
DRxC−/DRxC+
PD
R_EXT
HPD
SPDIF/I2S
SCLK/MCLK
LRCLK
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
V1P2
A
B
C
D
G
E
F
Type
I
I
I
I
I
I
O
O
O
O
O
P
P
I
I
I
I
I
BALL A1
CORNER
SPDIF/I
DDCSCL
DVDD
Tx2+
V3P3
GND
GND
1
1
2
S
SCLK/MCLK
DDCSDA
Description
MIPI/DSI Differential Clock.
Power-Down. Programmable polarity is determined at power-up. The I
the PD polarity are set by the PD pin state when the supplies are applied to the
ADV7533. Internally pulled up for 1; if 0 desired, pull down to ground with a 2 kΩ
resistor. Supports typical CMOS logic levels from 1.8 V up to 3.3 V.
Sets internal reference currents. Place a 1 KΩ resistor (1% tolerance) between this pin
and ground.
Hot Plug Detect Signal. Indicates to the interface whether the receiver is connected. 1.8
V to 5.0 V CMOS logic level.
S/PDIF or I
audio available through I
Audio Clock. Supports typical CMOS logic levels from1.8 V to 3.3 V. Unused input should
be connected to ground.
Audio Left/Right Clock Input. Supports typical CMOS logic levels from1.8 V to 3.3 V.
Unused input should be connected to ground.
Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel clock
rate; TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10× the pixel
clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock
rate; TMDS logic level.
Interrupt. CMOS logic level. A 2 kΩ pull-up resistor to interrupt the microcontroller I/O
supply is recommended. This is a low active signal.
1.8 V Power Supply for TMDS Outputs. Should be filtered and as quiet as possible.
Digital Logic Supply (1.2 V or 1.8 V). Set to 1.2 V for lowest power consumption. Should
be filtered and as quiet as possible.
MIPI/DSI Differential Pair for Lane 3. Unused channel should be connected to ground.
MIPI/DSI Differential Pair for Lane 2. Unused channel should be connected to ground.
MIPI/DSI Differential Pair for Lane 1.
MIPI/DSI Differential Pair for Lane 0.
DVDD
DRxC–
DRxC+
Tx2–
GND
2
Figure 4. Pin Configuration
LRCLK
DRx0–
DRx0+
V1P2
Tx1+
GND
PD
Rev. 0 | Page 9 of 12
(BALL SIDE DOWN)
3
2
S Audio Data Input. Represents the S/PDIF block or the two channels of
ADV7533
Not to Scale
TOP VIEW
DRx1–
DRx1+
AVDD
DVDD
V1P2
Tx1–
HPD
4
DRx2–
DRx2+
REXT
Tx0+
GND
SDA
INT
2
5
S. Supports typical CMOS logic levels from1.8 V to 3.3 V.
DRx3–
DRx3+
PVDD
Tx0–
GND
CEC
SCL
6
CECCLK
A2VDD
TxC+
TxC–
GND
GND
GND
7
2
C address and
ADV7533