ad8429 Analog Devices, Inc., ad8429 Datasheet - Page 16

• Manufacturer Part Number: ad8429
• Description: 1 Nv/hz Low Noise Instrumentation Amplifier Ad8429
• Manufacturer: Analog Devices, Inc.

AD8429
For best performance, maintain a source impedance to the REF
terminal that is well below 1 Ω. As shown in Figure 46, the
reference terminal, REF, is at one end of a 5 kΩ resistor.
Additional impedance at the REF terminal adds to this 5 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional R
can be calculated as follows:
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
INPUT VOLTAGE RANGE
Figure 4 and Figure 5 show the allowable common-mode input
voltage ranges for various output voltages and supply voltages.
The 3-op-amp architecture of the AD8429 applies gain in the
first stage before removing common-mode voltage with the
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 46) experience a
combination of a gained signal, a common-mode signal, and a
diode drop. This combined signal can be limited by the voltage
supplies even when the individual input and output signals are
not limited.
LAYOUT
To ensure optimum performance of the AD8429 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8429 are arranged in a logical manner to aid in
this task.
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To maintain high
CMRR over frequency, closely match the input source
impedance and capacitance of each path. Place additional
2(5 kΩ + R
V
INCORRECT
AD8429
REF
Figure 47. Driving the Reference Pin
REF
)/(10 kΩ + R
–IN
+IN
R
R
G
G
Figure 48. Pinout Diagram
1
2
3
4
(Not to Scale)
AD8429
TOP VIEW
REF
V
)
+
OP1177
–
8
7
6
5
CORRECT
+V
V
REF
–V
OUT
AD8429
S
S
REF
REF
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source resistance in the input path (for example, for input
protection) close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), choose a component
such that the parasitic capacitance is as small as possible.
Power Supplies and Grounding
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance. See
the PSRR performance curves in Figure 9 and Figure 10 for more
information.
Place a 0.1 μF capacitor as close as possible to each supply pin.
Because the length of the bypass capacitor leads is critical at
high frequency, surface-mount capacitors are recommended. A
parasitic inductance in the bypass ground trace works against
the low impedance created by the bypass capacitor. As shown in
Figure 49, a 10 μF capacitor can be used farther away from the
device. For larger value capacitors, intended to be effective at
lower frequencies, the current return path distance is less critical.
In most cases, this capacitor can be shared by other precision
integrated circuits.
A ground plane layer is helpful to reduce parasitic inductances.
This minimizes voltage drops with changes in current. The area
of the current path is directly proportional to the magnitude of
parasitic inductances and, therefore, the impedance of the path
at high frequency. Large changes in currents in an inductive
decoupling path or ground return create unwanted effects, due
to the coupling of such changes into the amplifier inputs.
Because load currents flow from the supplies, the load should
be connected at the same physical location as the bypass capa-
citor grounds.
Reference Pin
The output voltage of the AD8429 is developed with respect to
the potential on the reference terminal. Ensure that REF is tied
to the appropriate local ground.
Figure 49. Supply Decoupling, REF, and Output Referred to Local Ground
R
G
+IN
–IN
AD8429
+V
–V
S
S
0.1µF
0.1µF
REF
10µF
10µF
LOAD
V
OUT