adsp-21160n Analog Devices, Inc., adsp-21160n Datasheet - Page 13

• Manufacturer Part Number: adsp-21160n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Table 2. Pin Function Descriptions (continued)
Table 3. Boot Mode Selection
REV. 0
Pin
CLK_CFG3–0
CLKOUT
RESET
TCK
TMS
TDI
TDO
TRST
EMU
CIF
V
V
AV
AGND
GND
NC
EBOOT
1
0
0
0
0
1
DDINT
DDEXT
DD
LBOOT
0
0
1
0
1
1
Type
I
O/T
I/A
I
I/S
I/S
O
I/A
O (O/D)
O/T
P
P
P
G
G
BMS
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
Function
Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal
to n
For clock configuration definitions, see the RESET & CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.
CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can
be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled
on the ADSP-21160N with ID2-0 = 00x). Do not use CLKOUT in multiprocessing
systems; use CLKIN instead.
Processor Reset. Resets the ADSP-21160N to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
20 k internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21160N. TRST has a
20 k internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21160N emulator target board
connector only. EMU has a 50 k internal pull-up resistor.
Core Instruction Fetch. Signal is active low when an external instruction fetch is
performed. Driven by bus master only. Three-state when host is bus master. CIF has a
20 k internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
Core Power Supply. Nominally 1.9 V dc and supplies the DSP’s core processor
(40 pins).
I/O Power Supply. Nominally 3.3 V dc (43 pins).
Analog Power Supply. Nominally 1.9 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as V
circuitry is required. For more information, see Power Supplies
Analog Power Supply Return.
Power Supply Return (82 pins).
Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).
Booting Mode
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
–13–
DDINT
, except that added filtering
ADSP-21160N
on Page
8.