adsp-21990 Analog Devices, Inc., adsp-21990 Datasheet
adsp-21990
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adsp-21990 Summary of contents
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... TIMER 0 INTERRUPT WATCHDOG TIMER 1 FLAG CONTROLLER I/O TIMER (ICNTL) TIMER 2 Figure 1. Functional Block Diagram One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADSP-21990 ADDRESS EXTERNAL DATA MEMORY INTERFACE (EMI) CONTROL MEMORY DMA CONTROLLER ADC PIPELINE CONTROL FLASH ADC POR VREF www ...
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... ADSP-21990 TABLE OF CONTENTS General Description ................................................. 3 DSP Core Architecture ........................................... 3 Memory Architecture ............................................ 5 Bus Request and Bus Grant ..................................... 6 DMA Controller ................................................... 6 DSP Peripherals Architecture .................................. 7 Serial Peripheral Interface (SPI) Port ......................... 7 DSP Serial Port (SPORT) ........................................ 8 Analog-to-Digital Conversion System ........................ 8 Voltage Reference ................................................. 9 PWM Generation Unit ........................................... 9 Auxiliary PWM Generation Unit .............................. 9 Encoder Interface Unit ...
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... RAM, and 4K words (16-bit) of data RAM. Fabricated in a high speed, low power, CMOS process, the ADSP-21990 operates with a 6.25 ns instruction cycle time for a 160 MHz CCLK and with a 6.67 ns instruction cycle time for a 150 MHz CCLK. ...
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... DMA CONTROLLER SYSTEM INTERRUPT CONTROLLER Figure 2. Block Diagram counters and loop stacks, the ADSP-21990 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and pro- gram memory) ...
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... Boot memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permit- ting the ADSP-21990 to fetch two operands in a single cycle, one from program memory and one from data memory. The dual memory buses also let the embedded ADSP-21xx core fetch an operand from data memory and the next instruction from pro- gram memory in a single cycle ...
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... The bus request feature operates at all times, even while the DSP is booting and RESET is active. PAGES 32 TO 255 The ADSP-21990 asserts the BGH pin when it is ready to start 1024 WORDS/PAGE another external port access, but is held off because the bus was previously granted ...
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... SPISEL7) that are multiplexed with the PF1 to PF7 flag I/O lines. The SPISS input is used to select the ADSP-21990 as a slave to an external master. The SPISEL1 to SPISEL7 outputs can be used by the ADSP-21990 (acting as a master) to select/enable up to seven external slaves in a multidevice SPI configuration ...
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... HCLK. • The SPORT is capable of UART software emulation. ANALOG-TO-DIGITAL CONVERSION SYSTEM The ADSP-21990 contains a fast, high accuracy, multiple input analog-to-digital conversion system with simultaneous sam- pling capabilities. This analog-to-digital conversion system permits the fast, accurate conversion of analog signals needed in high performance embedded systems ...
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... At the 20 MHz sampling rate, the first data value is valid approximately 375 ns after the convert start command. All eight channels are converted in approximately 725 ns. The core of the ADSP-21990 provides 14-bit data such that the stored data values in the ADC data registers are 14 bits wide. VOLTAGE REFERENCE The ADSP-21990 contains an on-board band gap reference that can be used to provide a precise 1 ...
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... PWM generation unit of the ADSP-21990. WATCHDOG TIMER The ADSP-21990 integrates a watchdog timer that can be used as a protection mechanism against unintentional software events. It can be used to cause a complete DSP and peripheral reset in such an event. The watchdog timer consists of a 16-bit timer that is clocked at the external clock rate (CLKIN or crystal input frequency) ...
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... PERIPHERAL INTERRUPT CONTROLLER The peripheral interrupt controller is a dedicated peripheral 0x00 0100 unit of the ADSP-21990 (accessed via I/O mapped registers). The peripheral interrupt controller manages the connection of 0x00 0120 peripheral interrupt requests to the DSP core. For each peripheral interrupt source, there is a unique 4-bit ...
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... Power-down core • Power-down core/peripherals • Power-down all Idle Mode When the ADSP-21990 is in idle mode, the DSP core stops exe- cuting instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and periph- eral clock continue running. ...
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... POR, from the ADSP-21990 on power-up and if the power supply voltage falls below the threshold level. The ADSP-21990 may be reset from an external source using the RESET signal, or alterna- tively, the internal power-on reset circuit may be used by connecting the POR pin to the RESET pin ...
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... DEVELOPMENT TOOLS The ADSP-21990 is supported with a complete set of CROSSCORE™ software and hardware development tools, including Analog Devices emulators and VisualDSP++™ devel- opment environment. The emulator hardware that supports other ADSP-21xx DSPs also fully emulates the ADSP-21990 ...
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... File (LDF), allowing the developer to move between the graphi- cal and textual environments. DSP emulators from Analog Devices use the IEEE 1149.1 JTAG test access port of the ADSP-21990 processor to monitor and control the target board processor during emulation. The emu- lator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks ...
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... ADSP-21990 PIN FUNCTION DESCRIPTIONS ADSP-21990 pin definitions are listed in ADSP-21990 inputs are asynchronous and can be asserted asyn- chronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to V except for ADDR21–0, DATA15–0, PF7-0, and inputs that have internal pull-up or pull-down resistors (TRST, BMODE0, BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL, PWMSR, and RESET)— ...
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... Encoder Z Channel Input Encoder S Channel Input Auxiliary PWM Channel 0 Output Auxiliary PWM Channel 1 Output Auxiliary PWM Shutdown Pin Timer 0 Input/Output Pin Timer 1 Input/Output Pin Timer 2 Input/Output Pin PWM Channel A HI PWM PWM Channel A LO PWM Rev Page August 2007 ADSP-21990 ...
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... ADSP-21990 Table 4. Pin Descriptions (Continued) Name Type PWMSYNC D, BT PWMPOL PWMTRIP PWMSR AVDD (2 pins AVSS (2 pins VDDINT (6 pins VDDEXT (10 pins GND (16 pins Function PWM Channel B HI PWM ...
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... The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled. 2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK/ maximum MHz HCLK for the ADSP-21990BST order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL circuit and the associated frequency ratio ...
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... The I supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz, HCLK = 75 MHz DD for the ADSP-21990BBC. I refers only to the current consumption on the internal power supply lines (V DD power supply is very much dependent on the particular connection of the device in the final system. ...
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... The I supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 160 MHz, HCLK = 80 MHz DD for the ADSP-21990BST. I refers only to the current consumption on the internal power supply lines (V DD power supply is very much dependent on the particular connection of the device in the final system. ...
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... ADSP-21990 PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21990BBC Parameter Description ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL ...
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... PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21990BST Parameter Description ANALOG-TO-DIGITAL CONVERTER SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity ...
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... ADSP-21990 ABSOLUTE MAXIMUM RATINGS Table 5. Absolute Maximum Ratings Parameter 1 Internal (Core) Supply Voltage (V ) DDINT 1 External (I/O) Supply Voltage (V ) DDEXT 1, 2 Input Voltage (V – Output Voltage Swing (V – Load Capacitance ( Core Clock Period (t ) CCLK 1 Core Clock Frequency (f ) CCLK ...
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... CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160 MHz/80 MHz for the ADSP-21990BST and 150 MHz/75 MHz for the ADSP-21990BBC, when the peripheral clock rate is one-half the Table 6. Clock In and Clock Out Cycle Timing Parameter Timing Requirements ...
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... ADSP-21990 Programmable Flags Cycle Timing Table 7 and Figure 8 describe programmable flag operations. Table 7. Programmable Flags Cycle Timing Parameter Timing Requirement t Flag Input Hold Is Asynchronous HFI Switching Characteristics t Flag Output Delay with Respect to CLKOUT DFO t Flag Output Hold After CLKOUT High HFO ...
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... Timer Pulse Width Output HTO 1 The minimum time for t is one cycle, and the maximum time for t HTO HCLK PWM_OUT 1 32 equals (2 –1) cycles. HTO t HTO Figure 9. Timer PWM_OUT Cycle Timing Rev Page August 2007 ADSP-21990 Min Max 32 12.5 (2 –1) cycles Unit ns ...
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... ADSP-21990 External Port Write Cycle Timing Table 9 and Figure 10 describe external port write operations. The external port lets systems extend read/write accesses in three ways: wait states, ACK input, and combined wait states and ACK. To add waits with ACK, the DSP must see ACK low Table 9 ...
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... CSWS MS3–0 IOMS BMS A21–0 t AWS WR ACK t CDA t DWSAK D15–0 RD Figure 10. External Port Write Cycle Timing Rev Page August 2007 AKW t DSW ADSP-21990 t WSCS t WSA t WWR t CDD t DHW ...
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... ADSP-21990 External Port Read Cycle Timing Table 10 and Figure 11 describe external port read operations. For additional information on the ACK signal, see the discus- sion on Page 28. Table 10. External Port Read Cycle Timing 1, 2 Parameter Timing Requirements t ACK Strobe Pulse Width AKW t RD Asserted to Data Access Setup ...
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... CSRS MS3–0 IOMS BMS A21–0 t ARS RD t DRSAK ACK D15–0 WR Figure 11. External Port Read Cycle Timing Rev Page August 2007 AKW t t CDA RDA t ADA t SDA ADSP-21990 t RSCS t RSA t RWR ...
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... ADSP-21990 External Port Bus Request/Grant Cycle Timing Table 11 and Figure 12 describe external port bus request and bus grant operations. Table 11. External Port Bus Request and Grant Cycle Timing 1, 2 Parameter Timing Requirements t BR Asserted to CLKOUT High Setup BS t CLKOUT High to BR Deasserted Hold Time ...
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... Referenced to sample edge. 4 Referenced to drive edge. describe SPORT RFS Setup Before RCLK Rev Page August 2007 ADSP-21990 Min Max Unit 1 0.5t – HCLK 2t ns HCLK ...
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... ADSP-21990 5 Only applies to SPORT. 6 MCE=1, TFS enable, and TFS valid follow t DDTENFS 7 If external RFSD/TFS setup to RCLK/TCLK > 0.5t DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t HOFSE t SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. ...
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... TCLK t SFSE / I TFS t DTENLFSE 1ST BIT DT t DDTLFSE Figure 14. Serial Port—External Late Frame Sync (Frame Sync Setup > 0.5t Rev Page August 2007 DRIVE t HOSFSE DDTE HDTE/ I 2ND BIT DRIVE t HOSFSE DDTE / I t HDTE/ I 2ND BIT ) SCLK ADSP-21990 ...
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... ADSP-21990 EXTERNAL RFS WITH MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT Figure 15. Serial Port—External Late Frame Sync (Frame Sync Setup < 0.5t DRIVE SAMPLE DRIVE t t SFSE/ I HOFSE DDTE / I DTENLFSE t HDTE/ I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t t HOFSE/ I ...
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... DDSPID HDSPID MSB t t HSPID SSPID MSB VALID t DDSPID MSB t HSPID LSB VALID Figure 16. Serial Peripheral Interface (SPI) Port—Master Timing Rev Page August 2007 ADSP-21990 Min Max – 3 HCLK 2t – 3 HCLK 2t – 3 HCLK 4t – 1 HCLK 2t – 3 HCLK 2t – ...
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... ADSP-21990 Serial Peripheral Interface Port—Slave Timing Table 14 and Figure 17 describe SPI port slave operations. Table 14. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period SPICLK t Last SPICLK Edge to SPISS Not Asserted ...
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... TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS TCK t t STAP HTAP t DTDO t SSYS t DSYS Figure 18. JTAG Port Timing Rev Page August 2007 ADSP-21990 Min Max Unit TCK HSYS ...
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... ADSP-21990 POWER DISSIPATION Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: • ...
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... L L first calculate t on Page ADSP-21990 output voltage and the input threshold for the device requiring the hold time. A typical 'V will be 0 the total bus capacitance (per data line), and I age or three-state current (per data line). The hold time will be t plus the minimum disable time (i ...
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... ADSP-21990 PIN CONFIGURATIONS Table 17 identifies the signal for each CSP_BGA ball number. Table 17. 196-Ball CSP_BGA Ball Number by Signal Pin Name Ball No. Pin Name A0 N1 CONVST A10 H1 D9 A11 ...
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... CLKIN L14 MS3 CLKOUT G14 nc CML C9 nc Ball No. Pin Name Ball No. K3 PF9 B13 L3 PF10 C11 M3 PF11 C12 H3 PF12 C13 A1 PF13 B14 A14 PF14 C14 Rev Page August 2007 ADSP-21990 Pin Name Ball No. VIN5 C6 VIN6 B5 VIN7 C5 VREF XTAL F14 ...
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... ADSP-21990 Table 18 identifies the CSP_BGA ball number for each signal name. Table 18. 196-Ball CSP_BGA Signal by Ball Number Ball No. Pin Name Ball No D10 A4 RFS D11 A5 VIN4 D12 A6 BSHAN D13 A7 VIN0 D14 A8 VIN1 E1 A9 VIN3 E2 A10 PF0/SPISS E3 A11 PF4/SPISEL4 ...
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... Ball No. D3 IOMS G10 D4 ACK G11 D5 AVDD G12 D6 AVDD G13 D7 AVSS G14 Pin Name Ball No. Pin Name nc L3 MS1 GND L4 VDDEXT TMR1 L5 VDDINT CONVST L6 VDDEXT CLKOUT L7 VDDINT Rev Page August 2007 ADSP-21990 Ball No. Pin Name P10 D0 P11 BL P12 BH P13 nc P14 nc ...
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... ADSP-21990 Table 19 identifies the signal for each LQFP lead. Table 19. 176-Lead LQFP Signal by Lead Number Lead No. Signal Lead No VDDEXT 47 4 RCLK 48 5 SCK 49 6 MISO 50 7 MOSI ACK BGH ...
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... PF7/SPISEL7 138 148 PF8 137 175 PF9 136 171 POR 105 170 PWMPOL 85 121 PWMSR 86 120 PWMSYNC 84 Rev Page August 2007 ADSP-21990 Signal Lead No. PWMTRIP 87 RCLK RESET 106 RFS 172 SCK 5 SENSE 157 TCK 104 TCLK 174 TDI ...
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... ADSP-21990 OUTLINE DIMENSIONS 15.00 1.85 TOP VIEW 1.70 1.55 0.55 NOM 0.70 0.60 0.50 BALL DIAMETER NOTES: 1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 3. DIMENSIONS COMPLY WITH JEDEC STANDARD MO-192 VARIATION AAE-1 WITH THE EXCEPTION OF MAXIMUM HEIGHT ...
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... BSC LEAD PITCH DIMENSIONS SHOWN IN MILLIMETERS Figure 23. 176-Lead LQFP (ST-176) 1 Instruction Rate Operating Voltage Package Description 150 MHz 2.5 Int. V/3.3 Ext. V 160 MHz 2.5 Int. V/3.3 Ext. V 160 MHz 2.5 Int. V/3.3 Ext. V Rev Page August 2007 ADSP-21990 26.20 26.00 SQ 25.80 133 132 24.20 24.00 SQ TOP VIEW 23.80 (PINS DOWN ...
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... ADSP-21990 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02893-0-8/07(A) Rev Page August 2007 ...