adsp-2196m Analog Devices, Inc., adsp-2196m Datasheet - Page 10

• Manufacturer Part Number: adsp-2196m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2196
PC stack can generate a stack-level interrupt if the PC stack
falls below three locations full or rises above 28
locations full.
The following instructions globally enable or disable
interrupt servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG
and computational registers exist. Switching between the
primary and secondary registers lets programs quickly
service interrupts, while preserving the DSP’s state.
DMA Controller
The ADSP-2196 has a DMA controller that supports
automated data transfers with minimal overhead for the
DSP core. Cycle stealing DMA transfers can occur between
the ADSP-2196’s internal memory and any of its
DMA-capable peripherals. Additionally, DMA transfers
can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interface. DMA-capable peripherals include the
Host port, SPORTs, SPI ports, and UART. Each individual
DMA-capable peripheral has a dedicated DMA channel. To
describe each DMA sequence, the DMA controller uses a
set of parameters—called a DMA descriptor. When succes-
sive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one
DMA sequence auto-initiates and starts the next sequence.
DMA sequences do not contend for bus access with the DSP
core, instead DMAs “steal” cycles to access memory.
All DMA transfers use the DMA bus shown in the func-
tional block diagram
peripherals use the same bus, arbitration for DMA bus
access is needed. The arbitration for DMA bus access
appears in
Table 4. I/O Bus Arbitration Priority
10
DMA Bus Master
SPORT0 Receive DMA
SPORT1 Receive DMA
SPORT2 Receive DMA
SPORT0 Transmit DMA
SPORT1 Transmit DMA
SPORT2 Transmit DMA
SPI0 Receive/Transmit DMA
SPI1 Receive/Transmit DMA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Table
4.
on page
1. Because all of the
For current information contact Analog Devices at 800/262-5643
Arbitration Priority
0—Highest
1
2
3
4
5
6
7
Table 4. I/O Bus Arbitration Priority (Continued)
Host Port
The ADSP-2196’s Host port functions as a slave on the
external bus of an external Host. The Host port interface
lets a Host read from or write to the DSP’s memory space,
boot space, or internal I/O space. Examples of Hosts include
external microcontrollers, microprocessors, or ASICs.
The Host port is a multiplexed address and data bus that
provides both an 8-bit and a 16-bit data path and operates
using an asynchronous transmission protocol. Through this
port, an off-chip Host can directly access the DSP’s entire
memory space map, boot memory space, and internal I/O
space. To access the DSP’s internal memory space, a Host
steals one cycle per access from the DSP. A Host access to
the DSP’s external memory uses the external port interface
and does not stall (or steal cycles from) the DSP’s core.
Because a Host can access internal I/O memory space, a
Host can control any of the DSP’s I/O mapped peripherals.
The Host port is most efficient when using the DSP as a
slave and uses DMA to automate the incrementing of
addresses for these accesses. In this case, an address does
not have to be transferred from the Host for every
data transfer.
Host Port Acknowledge (HACK) Modes
The Host port supports a number of modes (or protocols)
for generating a HACK output for the host. The host selects
ACK or Ready Modes using the HACK_P and HACK pins.
The Host port also supports two modes for address control:
Address Latch Enable (ALE) and Address Cycle Control
(ACC) modes. The DSP auto-detects ALE versus ACC
Mode from the HALE and HWR inputs.
The host port HACK signal polarity is selected (only at
reset) as active high or active low, depending on the value
driven on the HACK_P pin.The HACK polarity is stored
into the host port configuration register as a read only bit.
The DSP uses HACK to indicate to the Host when to
complete an access. For a read transaction, a Host can
proceed and complete an access when valid data is present
in the read buffer and the host port is not busy doing a write.
For a write transactions, a Host can complete an access
when the write buffer is not full and the host port is not busy
doing a write.
DMA Bus Master
UART Receive DMA
UART Transmit DMA
Host Port DMA
Memory DMA
September 2001
Arbitration Priority
8
9
10
11—Lowest
REV. PrA