adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 21

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
The VCO frequency is calculated as follows:
f
f
where:
f
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 2, 4, 8, or 16 based on the divider value programmed on
the PMCTL register. During reset this value is 2.
f
VCO
VCO
CCLK
VCO
INPUT
• The product of CLKIN and PLLM must never exceed 1/2 of
• The product of CLKIN and PLLM must never exceed f
f
(INDIV = 0).
(max) in
(INDIV = 1).
XTAL
= 2 × PLLM × f
= VCO output
specified in
VCO
= (2 × PLLM × f
= is the input frequency to the PLL.
(max) in
BUF
CLKIN
Table 15
4096 CLKIN
DELAY OF
CYCLES
Table
Table 15
INPUT
INPUT
if the input divider is enabled
15.
DIVIDER
PMCTL
CLKIN
(INDIV)
) ÷ PLLD
if the input divider is not enabled
f
INPUT
Figure 4. Core Clock and System Clock Relationship to CLKIN
CLK_CFGx/PMCTL (2xPLLM)
FILTER
LOOP
MULTIPLIER
Rev. PrA | Page 21 of 66 | March 2010
PLL
PLL
CLKOUT (TEST ONLY)
VCO
VCO
f
VCO
ADSP-21483/21486/21487/21488/21489
DIVIDER
PMCTL
(PLLD)
PLL
f
f
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table
peripherals are defined in relation to t
specific section for each peripheral’s timing information.
Table 13. Clock Periods
Figure 4
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.
INPUT
INPUT
Timing
Requirements
t
t
t
t
CK
CCLK
PCLK
SDCLK
13. All of the timing specifications for the ADSP-2148x
f
= CLKIN when the input divider is disabled or
= CLKIN ÷ 2 when the input divider is enabled
CCLK
shows core to CLKIN relationships with external oscil-
(PLLBP)
PMCTL
CCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t
SDRAM Clock Period = (t
(SDCKR)
DIVIDER
SDRAM
PMCTL
DIVIDE
BY 2
BUF
PCLK
PCLK
. See the peripheral
(PLLBP)
PMCTL
PCLK
CCLK
CCLK
SDCLK
) × SDCKR
CCLK