adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 53

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
OUTPUT DRIVE CURRENTS
Figure 39
ers of the ADSP-21462W/ADSP-21465W/ADSP-21467. The
curves represent the current drive capability of the output driv-
ers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 15 on Page 25
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in
Timing is measured on signals when they cross the 1.5 V level as
described in
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
how output delays and holds vary with load capacitance. The
graphs of
Figure 39. ADSP-21462W/ADSP-21465W/ADSP-21467 Typical Drive at Junc-
12
10
8
4
6
2
0
OUTPUT
Figure 41. Voltage Reference Levels for AC Measurements
0
INPUT
Figure
shows typical I-V characteristics for the output driv-
OR
Figure
1.5V
42,
50
Figure
41. All delays (in nanoseconds) are mea-
through
Figure
Figure
tion Temperature
TBD
40.
100
43, and
40).
Table 46 on Page
Figure 44
Figure 44
150
shows graphically
200
may not be linear
51. These include
Rev. PrA | Page 53 of 60 | November 2008
1.5V
250
ADSP-21462W/ADSP-21465W/ADSP-21467
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
V
12
10
LOAD
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
4pF
8
6
4
2
0
Figure 40. Equivalent Device Loading for AC Measurements
0
Figure 42. Typical Output Rise/Fall Time (20% to 80%,
50
70
50
400
2pF
50
(Includes All Fixtures)
45
0.5pF
TBD
V
100
DD_EXT
TESTER PIN ELECTRONICS
= Max)
ZO = 50 (impedance)
TD = 4.04
150
T1
1.18 ns
200
OUTPUT
DUT
250