xa3s50 Xilinx Corp., xa3s50 Datasheet
xa3s50
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xa3s50 Summary of contents
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... NREs, the lengthy development cycles, and problems with obsolescence. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary. Table 1: Summary of Spartan-3 FPGA Attributes (One CLB = Four Slices) System Logic Device Gates Cells Rows Columns Total CLBs XA3S50 50K 1,728 16 XA3S200 200K 4,320 24 XA3S400 400K 8,064 32 ...
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... These elements are organized as shown in of IOBs surrounds a regular array of CLBs. The XA3S50 has a single column of block RAM embedded in the array. Those devices ranging from the XA3S200 to the XA3S1500 have two columns of block RAM. Each column is made up of several 18 Kbit RAM blocks ...
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... R Notes: 1. The XA3S50 has only the block RAM column on the far left. Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board ...
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R Table 2: Signal Standards Supported by the Spartan-3 Family Standard Description Category Single-Ended GTL Gunning Transceiver Logic HSTL High-Speed Transceiver Logic LVCMOS Low-Voltage CMOS LVTTL Low-Voltage Transistor-Transistor Logic PCI Peripheral Component Interconnect SSTL Stub Series Terminated Logic Differential LDT ...
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... R Table 3: Spartan-3 XA I/O Chart VQG100 Device Grade User Diff XA3S50 I XA3S200 I XA3S400 I XA3S1000 I XA3S1500 Notes: 1. All device options listed in a given package column are pin-compatible. DC Specifications Table 4: General Recommended Operating Conditions Symbol Description T Junction temperature J V Internal supply voltage CCINT ...
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... DS314 (v1.3) June 18, 2009 Product Specification Device XA3S50 XA3S200 XA3S400 XA3S1000 XA3S1500 XA3S50 XA3S200 XA3S400 XA3S1000 XA3S1500 XA3S50 XA3S200 XA3S400 XA3S1000 XA3S1500 of = 1.26V 3.45V, and V CCINT CCO provides quick, approximate, typical estimates, and does not is applied before V CCINT CCAUX ...
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... R Pb-Free Packaging For additional information on Pb-free packaging, see Packages. Example: XA3S50 - 208 Q Device Type Speed Grade Package Type Table 6: Package Types and Number of Pins Device Speed Grade Standard XA3S50 -4 Performance XA3S200 XA3S400 XA3S1000 XA3S1500 Additional Resources • DS099, Spartan-3 FPGA Family Data Sheet • ...
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R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ...