XC3S50A Xilinx Corp., XC3S50A Datasheet

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... Suspend Mode Timing - Device DNA Timing - Configuration and JTAG Timing Module 4: Pinout Descriptions DS529-4 (v1.5) July 10, 2007 • Pin Descriptions • Package Overview • Pinout Tables • Footprint Diagrams Spartan-3A FPGA XC3S50A XC3S200A XC3S400A XC3S700A XC3S1400A www.xilinx.com Status P RODUCTION P RODUCTION P RODUCTION P RODUCTION P RODUCTION ...

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Data Sheet 2 www.xilinx.com R DS529 July 10, 2007 Product Specification ...

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... Up to 502 I/O pins or 227 differential signal pairs ♦ LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O ♦ 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling Table 1: Summary of Spartan-3A FPGA Attributes System Equivalent Device Gates Logic Cells Rows Columns XC3S50A 50K 1,584 16 XC3S200A 200K 4,032 32 XC3S400A 400K 8,064 40 XC3S700A ...

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... IOBs Notes: 1. The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column. 4 • Digital Clock Manager (DCM) Blocks provide ...

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... Additionally, each Spartan-3A FPGA contains a unique, factory-programmed Device DNA identifier useful for tracking purposes, anti-cloning designs protection. Table 2: Available User I/Os and Differential (Diff) I/O Pairs TQ144 TQG144 Device User Diff 108 50 XC3S50A (7) (24) XC3S200A - - XC3S400A - - XC3S700A - - ...

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... Genealogy The “5C” and “4I” Speed Grade/Temperature Range part combinations may be dual marked as “5C/4I” SPARTAN TM XC3S50A Package TQ144AGQ0625 D1234567A 4C Pin P1 R SPARTAN R TM XC3S50A FT256 AGQ0625 Package D1234567A 4C www.xilinx.com Industrial Standard (–4) Production Production (v1.35) (v1.35) Production Production (v1.35) (v1.35) Production Production (v1 ...

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... The –5 speed grade is exclusively available in the Commercial temperature range. Revision History The following table shows the revision history for this document. Date Version 12/05/06 1.0 Initial release. 02/02/07 1.1 Promoted to Preliminary status. Updated maximum differential I/O count for XC3S50A in Updated differential input-only pin counts in 03/16/07 1.2 Minor formatting updates. 04/23/07 1.3 Added 05/08/07 1.4 Updated XC3S400A to Production ...

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Introduction and Ordering Information 8 www.xilinx.com R DS529-1 (v1.4.1) July 10, 2007 Product Specification ...

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... SRL16 Shift Registers - Carry and Arithmetic Logic ♦ I/O Resources ♦ Embedded Multiplier Blocks ♦ Programmable Interconnect ♦ ISE™ Software Design Tools ♦ IP Cores ♦ Embedded Processing and Control Solutions ♦ Pin Types and Package Overview ♦ Package Drawings ♦ Powering FPGAs ♦ ...

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Functional Description Related Product Families The Spartan-3AN nonvolatile FPGA family is architecturally identical to the Spartan-3A FPGA family, except that it has in-system flash memory and is offered in select pin-compatible package options. • DS557: Spartan-3AN FPGA Family Data Sheet ...

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R DS529-3 (v1.5) July 10, 2007 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...

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DC and Switching Characteristics Power Supply Specifications Table 5: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes ...

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R General Recommended Operating Conditions Table 8: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX T Input signal transition time IN Notes: ...

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DC and Switching Characteristics General DC Characteristics for I/O Pins Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins, FPGA powered I Leakage ...

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... XC3S200A XC3S400A 15 XC3S700A 25 XC3S1400A 30 XC3S50A 0.2 XC3S200A 0.2 XC3S400A 0.3 XC3S700A 0.3 XC3S1400A 0.3 XC3S50A 4.5 XC3S200A XC3S400A 12 XC3S700A 14 XC3S1400A 18 Table 8. = 1.26V 3.6V, and V = 3.6V. The FPGA is programmed with a “blank” configuration data CCO CCAUX provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower www.xilinx.com ...

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DC and Switching Characteristics Single-Ended I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 (4) LVCMOS18 1.65 (4) ...

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R Table 12: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions I I IOSTANDARD OL OH Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – ...

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DC and Switching Characteristics Differential I/O Standards Differential Input Pairs Internal Logic V V GND level Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) (3) LVDS_25 2.25 (3) LVDS_33 3.0 ...

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R Differential Output Pairs Internal Logic V OUTN V OUTP GND level Table 14: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute Min (mV) Typ (mV) Max (mV) LVDS_25 247 LVDS_33 247 BLVDS_25 240 MINI_LVDS_25 300 MINI_LVDS_33 ...

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DC and Switching Characteristics External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards 2.5V CCO CCO LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33 PPDS_25 a) Input-only differential pairs or pairs not ...

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R Device DNA Data Retention, Read Endurance Table 15: Device DNA Identifier Memory Characteristics Symbol DNA_RETENTION Data retention. Number of READ operations or JTAG ISC_DNA read operations. Unaffected by DNA_CYCLES HOLD or SHIFT operations. DS529-3 (v1.5) July 10, 2007 Product ...

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... ISE 9.2i; XC3S400A, all speed grades and all previously temperature grades, upgraded to Production Answer Record AR24992 XC3S50A, XC3S200A, XC3S700A, Answer XC3S1400A, all speed grades and all Record temperature grades, upgraded to AR24992 Production. XC3S700A and XC3S1400A -4 speed grade upgraded to Production. Updated pin-to-pin timing numbers. ...

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... XC3S50A output drive, Fast slew XC3S200A (3) rate, with DCM XC3S400A XC3S700A XC3S1400A (2) LVCMOS25 , 12mA XC3S50A output drive, Fast slew XC3S200A rate, without DCM XC3S400A XC3S700A XC3S1400A Table 26 and are based on the operating conditions set forth in www.xilinx.com DC and Switching Characteristics Speed Grade ...

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... XC3S1400A (3) LVCMOS25 , XC3S50A IFD_DELAY_VALUE = 0, XC3S200A (4) with DCM XC3S400A XC3S700A XC3S1400A (3) LVCMOS25 , XC3S50A IFD_DELAY_VALUE = 5, XC3S200A without DCM XC3S400A XC3S700A XC3S1400A Table 26 and are based on the operating conditions set forth in Table 22. If this is true of the data Input, add the Table www.xilinx.com Speed Grade -5 ...

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R Input Setup and Hold Times Table 20: Setup and Hold Times for the IOB Input Path Symbol Description Setup Times T Time from the setup of data at the IOPICK Input pin to the active transition at the ICLK ...

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DC and Switching Characteristics Input Propagation Times Table 21: Propagation Times for the IOB Input Path Symbol Description Propagation Times T The time it takes for data to travel IOPLI from the Input pin through the IFF latch to the ...

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R Input Timing Adjustments Table 22: Input Timing Adjustments by IOSTANDARD Adjustment Below Convert Input Time from LVCMOS25 to the Following Speed Grade Signal Standard (IOSTANDARD) -5 Single-Ended Standards LVTTL 0.62 LVCMOS33 0.54 LVCMOS25 0 LVCMOS18 0.83 LVCMOS15 0.60 LVCMOS12 ...

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DC and Switching Characteristics Output Propagation Times Table 23: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output IOCKP Flip-Flop (OFF), the time from the active transition at the OCLK input to data ...

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R Three-State Output Propagation Times Table 24: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK IOCKHZ input of the Three-state Flip-Flop (TFF) to when the Output pin ...

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DC and Switching Characteristics Output Timing Adjustments Table 25: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...

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R Table 25: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow ...

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DC and Switching Characteristics Table 25: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 ...

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R Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 26 lists the conditions to use for each standard. The method for measuring Input timing is as follows: A ...

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DC and Switching Characteristics Table 26: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V (V) REF SSTL3_I 1.5 SSTL3_II 1.5 Differential LVDS_25 - LVDS_33 - BLVDS_25 - MINI_LVDS_25 - MINI_LVDS_33 - LVPECL_25 - LVPECL_33 - RSDS_25 ...

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R The capacitive load ( connected between the output L and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based value of zero. High-impedance ...

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... SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality. Table 27: Equivalent V /GND Pairs per Bank CCO Device TQ144 XC3S50A 2 XC3S200A – XC3S400A – XC3S700A – XC3S1400A – ...

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R Table 28: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (V CCO TQ144 Top, Bottom Signal Standard (Banks (IOSTANDARD) 0,2) Single-Ended Standards LVTTL Slow ...

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DC and Switching Characteristics Table 28: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (V CCO TQ144 Top, Bottom Signal Standard (Banks (IOSTANDARD) 0,2) LVCMOS25 Slow – ...

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R Table 28: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (V CCO TQ144 Top, Bottom Signal Standard (Banks (IOSTANDARD) 0,2) Differential Standards (Number of I/O Pairs or Channels) LVDS_25 8 LVDS_33 8 BLVDS_25 1 MINI_LVDS_25 8 MINI_LVDS_33 ...

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DC and Switching Characteristics Configurable Logic Block (CLB) Timing Table 29: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time CKO from the active transition at the CLK input to data appearing at ...

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R Table 30: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on SHCKO the distributed RAM output Setup Times T Setup time of data at the BX ...

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DC and Switching Characteristics Clock Buffer/Multiplexer Switching Characteristics Table 32: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as ...

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Embedded Multiplier Timing Table 33 Embedded Multiplier Timing Symbol Combinatorial Delay T Combinational multiplier propagation delay from the A and B inputs MULT to the P outputs, assuming 18-bit inputs and a 36-bit ...

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DC and Switching Characteristics Block RAM Timing Table 34: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the active RCKO transition at the CLK input to data appearing at the DOUT output Setup ...

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R Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM ...

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DC and Switching Characteristics Table 36: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV ...

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R Digital Frequency Synthesizer (DFS) Table 37: Recommended Operating Conditions for the DFS Symbol (2) Input Frequency Ranges F CLKIN_FREQ_FX Frequency for the CLKIN input CLKIN (3) Input Clock Jitter Tolerance CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN input, based on ...

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DC and Switching Characteristics Table 38: Switching Characteristics for the DFS (Continued) Symbol Lock Time (2, 3) LOCK_FX The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when ...

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R Phase Shifter (PS) Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Operating Frequency Ranges PSCLK_FREQ Frequency for the PSCLK input (F ) PSCLK Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of ...

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DC and Switching Characteristics Miscellaneous DCM Timing Table 41: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN Minimum duration of a RST pulse width (2) DCM_RST_PW_MAX Maximum duration of a RST pulse width (3) DCM_CONFIG_LAG_TIME Maximum duration from V configuration successfully completed (DONE ...

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R Suspend Mode Timing Entering Suspend Mode SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPGA Outputs FPGA Inputs, Interconnect Table 43: Suspend Mode Timing Parameters Symbol Entering Suspend Mode T Rising edge of SUSPEND pin to falling edge ...

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... CCO Description , V , and V CCINT CCAUX CCO Table www.xilinx.com T ICCK DS529-3_01_112906 All Speed Grades Device Min Max All – 18 All 0.5 - XC3S50A – 0.5 XC3S200A – 0.5 XC3S400A – 1 XC3S700A – 2 XC3S1400A – 2 All 250 – All 0 This means power must be applied to all V DS529-3 (v1.5) July 10, 2007 ...

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R Configuration Clock (CCLK) Characteristics Table 45: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T ConfigRate setting CCLK1 T CCLK3 T CCLK6 T CCLK7 T CCLK8 T CCLK10 T CCLK12 T CCLK13 ...

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DC and Switching Characteristics Table 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol Description Equivalent CCLK clock frequency F by ConfigRate setting CCLK1 F CCLK3 F CCLK6 F CCLK7 F CCLK8 F CCLK10 F CCLK12 F CCLK13 ...

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R Master Serial and Slave Serial Mode Timing PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 12: Waveforms for Master Serial and Slave Serial Configuration Table 49: Timing for the Master Serial and Slave Serial Configuration Modes ...

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DC and Switching Characteristics Slave Parallel Mode Timing PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) Notes possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then ...

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R Serial Peripheral Interface (SPI) Configuration Timing PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK DIN (Input) CSO_B MOSI ...

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DC and Switching Characteristics Table 52: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input ...

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R Byte Peripheral Interface (BPI) Configuration Timing PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) M[2:0] <0:1:0> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B CCLK A[25:0] D[7:0] (Input) Shaded ...

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DC and Switching Characteristics Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol T Parallel NOR Flash PROM chip-select time ELQV T Parallel NOR Flash PROM output-enable time GLQV T Parallel NOR ...

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... All functions except those shown below Configuration commands (CFG_IN, ISC_PROGRAM) All functions except ISC_DNA command During ISC_DNA command All operations on XC3S50A, XC3S200A, and XC3S400A FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XC3S700A and XC3S1400A FPGAs, except for BYPASS or HIGHZ instructions Table 8 ...

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DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version 12/05/06 1.0 Initial release. 02/02/07 1.1 Promoted to Preliminary status. Moved timing specifications for the v1.32 speed files. Added recommended Simultaneous Switching ...

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... Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global clock inputs that optionally clock the entire device. The exceptions are the TQ144 and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half CLK of the device ...

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... FG676 23 14 Table 58: Maximum User I/O by Package Maximum User I/Os Device Package and Input-Only XC3S50A TQ144 108 XC3S50A 144 XC3S200A FT256 195 XC3S400A 195 XC3S200A 248 FG320 XC3S400A 251 64 Description A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/O ...

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... XPower Power Estimator calculator integrated in the Xilinx ISE development software. Table 59 provides the thermal characteristics for the various Table 59: Spartan-3A Package Thermal Characteristics Junction-to-Case Package Device TQ144 XC3S50A TQG144 XC3S50A FT256 XC3S200A FTG256 XC3S400A XC3S200A FG320 FGG320 XC3S400A XC3S400A FG400 ...

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... I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. The XC3S50A does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode. An electronic version of this package pinout table and ...

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R Table 60: Spartan-3A TQ144 Pinout (Continued) Bank Pin Name 2 IO_L05P_2 2 IO_L06N_2/D6 2 IO_L06P_2 2 IO_L07N_2/D4 2 IO_L07P_2/D5 2 IO_L08N_2/GCLK15 2 IO_L08P_2/GCLK14 2 IO_L09N_2/GCLK1 2 IO_L09P_2/GCLK0 2 IO_L10N_2/GCLK3 2 IO_L10P_2/GCLK2 2 IO_L11N_2/DOUT 2 IO_L11P_2/AWAKE 2 IO_L12N_2/D3 2 IO_L12P_2/INIT_B ...

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... Pinout Descriptions User I/Os by Bank Table 61 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQ144 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 61: User I/Os Per Bank for the XC3S50A in the TQ144 Package Package I/O Bank Maximum I/O Edge Top 0 ...

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R TQ144 Footprint Note pin 1 indicator in top-left corner and logo orientation. TMS 1 TDI 2 X IO_L02P_3 3 IO_L01P_3 4 IO_L02N_3 5 IO_L01N_3 6 IO_L03P_3 7 IO_L03N_3 8 GND 9 IO_L04P_3 10 IO_L04N_3/VREF_3 11 IO_L05P_3/LHCLK0 12 IO_L05N_3/LHCLK1 13 ...

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... Table 65 summarizes the Spartan-3A FPGA footprint migration differences for the FT256 package. The XC3S50A does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www ...

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... N.C. (◆) IO_L17N_1/A13 1 N.C. (◆) IO_L17P_1/A12 1 N.C. (◆) IO_L18N_1/A15 1 N.C. (◆) IO_L18P_1/A14 1 N.C. (◆) IO_L19N_1/A17 1 N.C. (◆) IO_L19P_1/A16 DS529-4 (v1.5) July 10, 2007 Product Specification Table 62: Spartan-3A FT256 Pinout (Continued) FT256 Ball Type Bank XC3S50A B5 VCCO 1 IO_L20N_1 B9 VCCO 1 IO_L20P_1 B13 VCCO 1 IO_L22N_1 E8 VCCO 1 IO_L22P_1 1 IO_L23N_1 N14 DUAL 1 IO_L23P_1 N13 ...

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... IP_2/VREF_2 IP_2/VREF_2 2 IP_2/VREF_2 IP_2/VREF_2 2 IP_2/VREF_2 IP_2/VREF_2 2 IP_2/VREF_2 IP_2/VREF_2 2 IP_2/VREF_2 IP_2/VREF_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 72 Table 62: Spartan-3A FT256 Pinout (Continued) FT256 Ball Type Bank XC3S50A 2 VCCO_2 T7 GCLK 3 IO_L01N_3 R7 GCLK 3 IO_L01P_3 3 IO_L02N_3 T8 GCLK 3 IO_L02P_3 P8 GCLK 3 IO_L03N_3 3 IO_L03P_3 P9 GCLK 3 N.C. (◆) N9 GCLK 3 N.C. (◆) 3 N.C. (◆ ...

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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND DS529-4 (v1.5) July 10, 2007 Product Specification Table 62: Spartan-3A FT256 Pinout (Continued) FT256 Ball Type Bank XC3S50A P2 I/O GND GND R1 I/O GND GND M4 I/O GND GND N3 I/O GND GND GND GND F4 VREF VCCAUX ...

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... FT256 package. The XC3S50A FPGA in the FT256 package has 51 unconnected balls, labeled with an “N.C.” type. These pins are also indicated in Figure 18. The AWAKE pin is counted as a Dual-Purpose I/O. Table 63: User I/Os Per Bank on XC3S50A in the FT256 Package Package I/O Bank Maximum I/O Edge Top 0 ...

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... I/O configured for the device on the right. I/O Differential I/O Alignment Differences I/O I/O Also, some differential I/O pairs on the XC3S50A FPGA are I/O aligned differently than the corresponding pairs on the XC3S200A or XC3S400A FPGAs, as shown in I/O the mismatched pairs are in I/O Bank 2. The shading I/O highlights the differences ...

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... Pinout Descriptions XC3S50A Does Not Have BPI Mode Address Out- puts The XC3S50A FPGA does not generate the BPI-mode address pins during configuration. Table 67 these differences. Table 67: XC3S50A BPI Functional Differences FT256 Bank XC3S50A Ball N16 IO_L03N_1 P16 IO_L03P_1 J13 IO_L10N_1 ...

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... L03P_2 L23P_3 M2 RDWR_B I/O I/O I/O T GND L02N_2 L04P_2 L05P_2 CSO_B VS2 (Differential Outputs) Figure 18: XC3S50A FT256 Package Footprint (top view) I/O: Unrestricted, general-purpose 53 user I/O INPUT: Unrestricted, 20 general-purpose input pin CONFIG: Dedicated configuration 3 pins, SUSPEND pin N.C.: Not connected (XC3S50A 51 only) DS529-4 (v1.5) July 10, 2007 Product Specification ...

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Pinout Descriptions FT256 Footprint (XC3S200A, XC3S400A I/O I/O A GND L19P_0 L18P_0 I/O I/O B TDI TMS L19N_0 L18N_0 I/O I/O I/O C GND L20P_0 L01N_3 L01P_3 VREF_0 I/O I/O I/O D VCCO_3 L03P_3 L02N_3 L02P_3 I/O ...

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R FG320: 320-ball Fine-pitch Ball Grid Array The 320-ball fine-pitch ball grid array package, FG320, supports two Spartan-3A FPGAs, the XC3S200A and the XC3S400A, as shown in Table 68 and The FG320 package array of ...

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Pinout Descriptions Table 68: Spartan-3A FG320 Pinout (Continued) Bank Pin Name 1 IO_L02N_1/LDC0 1 IO_L02P_1/LDC1 1 IO_L03N_1/A1 1 IO_L03P_1/A0 1 IO_L05N_1 1 IO_L05P_1 1 IO_L06N_1 1 IO_L06P_1 1 IO_L07N_1/VREF_1 1 IO_L07P_1 1 IO_L09N_1/A3 1 IO_L09P_1/A2 1 IO_L10N_1/A5 1 IO_L10P_1/A4 1 ...

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R Table 68: Spartan-3A FG320 Pinout (Continued) Bank Pin Name 2 IO_L14P_2/GCLK2 2 IO_L15N_2 2 IO_L15P_2 2 IO_L16N_2/MOSI/CSI_B 2 IO_L16P_2 2 IO_L17N_2 2 IO_L17P_2 2 IO_L18N_2/DOUT 2 IO_L18P_2/AWAKE 2 IO_L19N_2 2 IO_L19P_2 2 IO_L20N_2/D3 2 IO_L20P_2/INIT_B 2 IO_L21N_2 2 IO_L21P_2 ...

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Pinout Descriptions Table 68: Spartan-3A FG320 Pinout (Continued) Bank Pin Name 3 IP_L12P_3 3 IP_L16N_3 3 IP_L16P_3 3 IP_L20N_3 3 IP_L20P_3 3 IP_L24N_3 3 IP_L24P_3 3 IP_L28N_3 3 IP_L28P_3 3 IP_L32N_3/VREF_3 3 IP_L32P_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 ...

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R User I/Os by Bank Table 69 and Table 70 indicate how the available user-I/O pins are distributed between the four I/O banks on the FG320 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 69: User I/Os ...

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Pinout Descriptions FG320 Footprint I/O I/O I/O A GND L18N_0 L23N_0 L21N_0 VREF_0 I/O I/O I/O I/O B L02N_3 L02P_3 L23P_0 L21P_0 I/O I/O C TMS L01N_3 L01P_3 I/O I/O I/O D GND L07P_3 L03N_3 L03P_3 ...

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R FG400: 400-ball Fine-pitch Ball Grid Array The 400-ball fine-pitch ball grid array, FG400, supports two different Spartan-3A FPGAs, the XC3S400A and the XC3S700A. Both devices share a common footprint for this package as shown in Table 72 and Table ...

Page 86

Pinout Descriptions Table 72: Spartan-3A FG400 Pinout (Continued) Bank Pin Name 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0/VREF_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 1 ...

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R Table 72: Spartan-3A FG400 Pinout (Continued) Bank Pin Name 1 IP_L23P_1/VREF_1 1 IP_L27N_1 1 IP_L27P_1 1 IP_L31N_1 1 IP_L31P_1/VREF_1 1 IP_L35N_1 1 IP_L35P_1 1 IP_L39N_1 1 IP_L39P_1/VREF_1 SUSPEND 1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 ...

Page 88

Pinout Descriptions Table 72: Spartan-3A FG400 Pinout (Continued) Bank Pin Name 2 IP_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IO_L01N_3 3 ...

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R Table 72: Spartan-3A FG400 Pinout (Continued) Bank Pin Name 3 IP_L27N_3 3 IP_L27P_3 3 IP_L31N_3 3 IP_L31P_3 3 IP_L35N_3 3 IP_L35P_3 3 IP_L39N_3/VREF_3 3 IP_L39P_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND GND GND GND ...

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Pinout Descriptions User I/Os by Bank Table 73 indicates how the 311 available user-I/O pins are distributed between the four I/O banks on the FG400 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 73: User I/Os Per ...

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R THIS PAGE INTENTIONALLY LEFT BLANK DS529-4 (v1.5) July 10, 2007 Product Specification www.xilinx.com Pinout Descriptions 91 ...

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Pinout Descriptions FG400 Footprint Left Half of FG400 Package (top view) I/O: Unrestricted, 155 general-purpose user I/O INPUT: Unrestricted, 46 general-purpose input pin DUAL: Configuration, 52 AWAKE pins, then possible user I/O VREF: User I/O or input 26 voltage reference ...

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R Bank I/O I/O I/O GND VCCAUX L13N_0 L07N_0 L08N_0 I/O I/O I/O I/O GND L14P_0 L13P_0 L11P_0 L08P_0 I/O I/O I/O I/O I/O L10N_0 L14N_0 L11N_0 L07P_0 L06N_0 VREF_0 I/O I/O I/O I/O ...

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Pinout Descriptions FG484: 484-ball Fine-pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FG484, supports both the XC3S700A and the XC3S1400A FPGAs. There are three pinout differences, as described in Table 74 lists all the FG484 package pins. They ...

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R Table 74: Spartan-3A FG484 Pinout (Continued) Bank Pin Name 0 IO_L34N_0 0 IO_L34P_0 0 IO_L35N_0 0 IO_L35P_0 0 IO_L36N_0/PUDC_B 0 IO_L36P_0/VREF_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 ...

Page 96

Pinout Descriptions Table 74: Spartan-3A FG484 Pinout (Continued) Bank Pin Name 1 IO_L36N_1 1 IO_L36P_1 1 IO_L37N_1 1 IO_L37P_1 1 IO_L38N_1 1 IO_L38P_1 1 IO_L40N_1 1 IO_L40P_1 1 IO_L41N_1 1 IO_L41P_1 1 IO_L42N_1 1 IO_L42P_1 1 IO_L44N_1/A21 1 IO_L44P_1/A20 1 ...

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R Table 74: Spartan-3A FG484 Pinout (Continued) Bank Pin Name 2 IO_L20N_2/GCLK3 2 IO_L20P_2/GCLK2 2 IO_L21N_2 2 IO_L21P_2 2 IO_L22N_2/MOSI/CSI_B 2 IO_L22P_2 2 IO_L23N_2 2 IO_L23P_2 IO_L24N_2/ 2 DOUT 2 IO_L24P_2/AWAKE 2 IO_L25N_2 2 IO_L25P_2 2 IO_L26N_2/D3 2 IO_L26P_2/INIT_B 2 ...

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Pinout Descriptions Table 74: Spartan-3A FG484 Pinout (Continued) Bank Pin Name 3 IO_L12N_3 3 IO_L12P_3 3 IO_L13N_3 3 IO_L13P_3 3 IO_L14N_3 3 IO_L14P_3 3 IO_L16N_3 3 IO_L16P_3 3 IO_L17N_3/VREF_3 3 IO_L17P_3 3 IO_L18N_3 3 IO_L18P_3 3 IO_L20N_3 3 IO_L20P_3 3 ...

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R Table 74: Spartan-3A FG484 Pinout (Continued) Bank Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...

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Pinout Descriptions User I/Os by Bank Table 75 and Table 76 indicate how the user-I/O pins are distributed between the four I/O banks on the FG484 Table 75: User I/Os Per Bank for the XC3S700A in the FG484 Package Package ...

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R Footprint Migration Differences Table 77 summarizes any footprint and functionality differences between the XC3S700A and the XC3S1400A FPGAs that might affect easy migration between devices available in the FG484 package. There are three such balls. All other pins not ...

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Pinout Descriptions FG484 Footprint Left Half of FG484 Package (top view) I/O: Unrestricted, 194- general-purpose user I/O 195 INPUT: Unrestricted, 61- general-purpose input pin 62 DUAL: Configuration, 52 AWAKE pins, then possible user I/O VREF: User I/O or input 33- ...

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R Bank I/O I/O I/O I/O I/O I/O L18P_0 L12N_0 L16N_0 L13N_0 L12P_0 L10N_0 GCLK6 VREF_0 I/O I/O I/O GND GND VCCO_0 L16P_0 L13P_0 L10P_0 I/O I/O I/O I/O I/O I/O L17P_0 L15N_0 ...

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Pinout Descriptions FG676: 676-ball Fine-pitch Ball Grid Array The 676-ball fine-pitch ball grid array, FG676, supports the XC3S1400A FPGA. Table 78 lists all the FG676 package pins. They are sorted by bank number and then by pin name. Pairs of ...

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R Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name 0 IO_L38P_0 0 IO_L39N_0 0 IO_L39P_0 0 IO_L40N_0 0 IO_L40P_0 0 IO_L41N_0 0 IO_L41P_0 0 IO_L42N_0 0 IO_L42P_0 0 IO_L43N_0 0 IO_L43P_0 0 IO_L44N_0 0 IO_L44P_0 0 IO_L45N_0 0 IO_L45P_0 ...

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Pinout Descriptions Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name 1 IO_L12N_1 1 IO_L12P_1 1 IO_L13N_1 1 IO_L13P_1 1 IO_L14N_1 1 IO_L14P_1 1 IO_L15N_1 1 IO_L15P_1 1 IO_L17N_1 1 IO_L17P_1 1 IO_L18N_1 1 IO_L18P_1 1 IO_L19N_1 1 IO_L19P_1 1 ...

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R Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name 1 IP_L20N_1/VREF_1 1 IP_L20P_1 1 IP_L24N_1/VREF_1 1 IP_L24P_1 1 IP_L28N_1 1 IP_L28P_1/VREF_1 1 IP_L32N_1 1 IP_L32P_1 1 IP_L36N_1 1 IP_L36P_1/VREF_1 1 IP_L40N_1 1 IP_L40P_1 1 IP_L44N_1 1 IP_L44P_1/VREF_1 1 IP_L48N_1 ...

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Pinout Descriptions Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name 2 IO_L31P_2 2 IO_L32N_2/DOUT 2 IO_L32P_2/AWAKE 2 IO_L33N_2 2 IO_L33P_2 2 IO_L34N_2/D3 2 IO_L34P_2/INIT_B 2 IO_L35N_2 2 IO_L35P_2 2 IO_L36N_2/D1 2 IO_L36P_2/D2 2 IO_L37N_2 2 IO_L37P_2 2 IO_L38N_2 2 ...

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R Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name 3 IO_L05N_3 3 IO_L05P_3 3 IO_L06N_3 3 IO_L06P_3 3 IO_L07N_3 3 IO_L07P_3 3 IO_L09N_3 3 IO_L09P_3 3 IO_L10N_3 3 IO_L10P_3 3 IO_L11N_3 3 IO_L11P_3 3 IO_L13N_3 3 IO_L13P_3 3 IO_L14N_3 ...

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Pinout Descriptions Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name 3 IO_L57N_3 3 IO_L57P_3 3 IO_L59N_3 3 IO_L59P_3 3 IO_L60N_3 3 IO_L60P_3 3 IO_L61N_3 3 IO_L61P_3 3 IO_L63N_3 3 IO_L63P_3 3 IO_L64N_3 3 IO_L64P_3 3 IO_L65N_3 3 IO_L65P_3 3 ...

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R Table 78: Spartan-3A FG676 Pinout (Continued) Bank Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...

Page 112

Pinout Descriptions User I/Os by Bank Table 79 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FG676 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 79: User I/Os Per ...

Page 113

R Footprint Migration Differences The XC3S1400A FPGA is the only Spartan-3A device offered in the FG676 package. However, summarizes footprint and functionality differences between the XC3S1400A and the XC3SD1800A in the Spartan-3A DSP platform. There are 17 unconnected balls in ...

Page 114

Pinout Descriptions FG676 Footprint Left Half of FG676 Package (top view) I/O: Unrestricted, general-purpose user I/O 313 INPUT: Unrestricted, 67 general-purpose input pin DUAL: Configuration, 52 AWAKE pins, then possible user I/O VREF: User I/O or input voltage reference for ...

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R Bank I/O I/O I/O I/O GND INPUT L26N_0 L23N_0 L18N_0 L15N_0 L14N_0 GCLK7 I/O I/O I/O I/O I/O VCCO_0 L26P_0 L14P_0 L23P_0 L19N_0 L18P_0 L15P_0 GCLK6 VREF_0 I/O I/O I/O I/O GND ...

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... Version 12/05/06 1.0 Initial release. 02/02/07 1.1 Promoted to Preliminary status. Added DOUT pin to DUAL-type pins in DUAL pins and differential pairs in numbers P24 and P25 in XC3S50A and XC3S200A in the FT256 package, shown in to summarize the differences. 03/16/07 1.2 Corrected minor typographical error in 04/23/07 1.3 Added reference to compatible Spartan-3A DSP family. 05/08/07 1 ...