XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 26

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XC3S50A

Manufacturer Part Number
XC3S50A
Description
Spartan-3a Fpga Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

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DC and Switching Characteristics
Input Propagation Times
Table 21: Propagation Times for the IOB Input Path
26
Notes:
1.
2.
Propagation Times
Symbol
T
T
IOPLID
The numbers in this table are tested using the methodology presented in
Table 8
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from
IOPLI
and
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
Table
11.
Description
Table
LVCMOS25
LVCMOS25
22.
www.xilinx.com
Conditions
(2)
(2
Table 26
DELAY_
and are based on the operating conditions set forth in
VALUE
IFD_
0
1
2
3
4
5
6
7
8
Device
All
All
Max
1.38
2.12
3.07
3.87
4.42
4.25
5.18
6.01
6.56
-5
DS529-3 (v1.5) July 10, 2007
Speed Grade
Product Specification
Max
2.14
2.59
3.33
4.21
4.80
4.63
5.68
6.59
7.22
-4
Units
ns
ns
R

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