OPB16450UART Xilinx Corp., OPB16450UART Datasheet

OPB16450UART

Manufacturer Part Number

OPB16450UART

Description

Ds433 August 18, 2004 Product Specification

Manufacturer

Xilinx Corp.

Datasheet

1.OPB16450UART.pdf (15 pages)

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NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,

require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties

DS433 August 18, 2004

Introduction

This document provides the specification for the OPB Uni-

versal Asynchronous Receiver/Transmitter (UART) Intellec-

tual Property (IP).

The UART described in this document has been designed

incorporating the features described in National Semicon-

ductor PC16550D UART with FIFOs data sheet (June,

1995), (http://www.national.com/pf/PC/PC16550D.html).

The National Semiconductor PC16550D data sheet is refer-

enced throughout this document and should be used as the

authoritative

National Semiconductor implementation and the OPB

UART Point Design implementation are highlighted and

explained in

Features

•

DS433 August 18, 2004

Product Specification

application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may

Hardware and software register compatible with all

standard 16450 UARTs

Implements all standard serial interface protocols

Registers

Scratch Register

or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

5, 6, 7, or 8 bits per character

Odd, Even, or no parity detection and generation

1, 1.5, or 2 stop bit detection and generation

Internal baud rate generator and separate receiver

clock input

Modem control functions

False start bit detection and recovery

Prioritized transmit, receive, line status, and

modem control interrupts

Line break detection and generation

Internal loop back diagnostic functionality

Receiver Buffer Register (Read Only)

Transmitter Holding Register (Write Only)

Interrupt Enable Register

Interrupt Identification Register (Read Only)

Line Control and Line Status Registers

Modem Control and Modem Status Registers

Specification Exceptions

trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

specification.

Differences

between

www.xilinx.com

1-800-255-7778

the

OPB 16450 UART

Product Specification

Supported Device

Family

Version of Core

Slices

LUTs

FFs

Block RAMs

Documentation

Design File Formats

Constraints File

Verification

Instantiation

Template

Reference Designs

Xilinx Implementation

Tools

Verification

Simulation

Synthesis

Support provided by Xilinx, Inc.

Divisor Latch (least and more significant byte)

Design Tool Requirements

LogiCORE™ Facts

Provided with Core

Resources Used

Core Specifics

opb_uart16450

Virtex-II, QPro Virtex-II, Virtex-E,

Support

Virtex-II

ModelSim SE/EE 5.6e or later

Spartan-II

Virtex-II Pro

Product Specification.

341

357

347

Min

™

, Virtex-4

Spartan-3

5.1i or later

™

VHDL

None

XST

N/A

, Spartan-IIE

™

, Virtex

™

, QPro

v1.00c

Max

341

357

347

™

-R

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