OPB16450UART Xilinx Corp., OPB16450UART Datasheet - Page 12

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OPB16450UART

Manufacturer Part Number
OPB16450UART
Description
Ds433 August 18, 2004 Product Specification
Manufacturer
Xilinx Corp.
Datasheet
OPB 16450 UART
Divisor (Most Significant Byte) Register
As shown in
counter.
UART
The top-level block diagram for the UART is shown in
12
Table 15: Divisor (Most Significant Byte) Register Bit Definitions
Location
7-0
Bit
Block Diagram
Table
OPB
Name
15, the Divisor (Most Significant Byte) Register holds the most significant byte of the baud rate generator
DLM
SRAM
IPIF
Read/Write
Access
DDIS
Figure 1: UART Top-level Block Diagram
RBR/FIFO
THR/FIFO
Reset Value
“00000000”
MCR
LCR
MSR
SCR
LSR
IER
DLM
DLL
IIR
Figure
www.xilinx.com
1-800-255-7778
1.
Divisor Most Significant Byte.
CTSN DSRN DCDN RIN
Baud Generator
MODEM
LOGIC
Transmitter
Receiver
RCLK
Description
RXRDYN
BAUDOUTN
TXRDYN
OUT1N
OUT2N
XOUT
DTRN
SOUT
RTSN
SIN
XIN
DS433 August 18, 2004
Product Specification

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