XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 62

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
62
12/05/06
02/02/07
03/16/07
04/23/07
05/08/07
07/10/07
Date
Version
1.0
1.1
1.2
1.3
1.4
1.5
Initial release.
Promoted to Preliminary status. Moved
timing specifications for the v1.32 speed files. Added recommended Simultaneous Switching Output (SSO)
limits in
input during the ISC_DNA command, affecting both
Requirements for Differential I/O."
wording in
Updated all AC timing specifications to the v1.34 speeds file. Promoted the XC3S700A and XC3S1400A
FPGAs offered in the -4 speed grade to Production status, as shown in
regarding the extra logic (one LUT) automatically added by ISE 9.1i and later software revisions for any DCM
application that leverages the Digital Frequency Synthesizer (DFS). Separated some JTAG specifications by
array size or function, as shown in
Updated all AC timing specifications to the v1.35 speeds file. Promoted all family members except the
XC3S400A to Production status, as shown in
Updated XC3S400A to Production and v1.36 speeds file. Added banking rules and other explanatory
footnotes to
Pin-to-Pin Clock-to-Output times in
Updated TIOICKPD for -5 in
Embedded Multiplier Hold Times in
T
Added DIFF_HSTL_I and DIFF_HSTL_III to
characteristics in
pin-to-pin setup and hold times in
Method values in
and added hold times to
CLKOUT_PER_JITT_2X and CLKOUT_PER_JITT_DV2 in
Commercial in
TDITCK
Table
and F
Table 51
Table 12
28. Set a 10 μs maximum pulse width for the DNA_PORT READ signal and the JTAG clock
TCK
Table 45
Table
Table
performance for XC3S400A in
and
and
26. Added BLVDS SSO numbers
14. Updated for speed file v1.37 in ISE 9.2.01i as shown in
through
Table
Table
Table
Table
53; no specifications affected.
33. Updated block RAM clock width in
www.xilinx.com
13. Corrected DIFF_SSTL3_II V
Table
Table
Added separate DIN hold time for Slave mode in
Table
20. Added SSO numbers to
Table
Table
47.
Table 15
19. Updated TMDS output adjustment in
55. Updated quiescent current limits in
18. Updated XC3S400A Pin-to-Pin Setup Times in
33. Improved CLKOUT_FREQ_CLK90 in
Table
Table
to under
Revision
Table
13,
Table 42
16.
Table
55.
inTable
"DC Electrical Characteristics"
Table
14,
and
Table 27
Table
28. For Multiplier block, updated setup times
OL
Table
36. Added CCLK specifications for
Max in
Table
26, and
55. Described
Table
and
Table
34. Updated
Table
16. Added Note 2 to
Table
DS529-3 (v1.5) July 10, 2007
Table
Table
14. Improved XC3S400A
28. Removed invalid
Table
Table
Table
28. Updated TMDS DC
Product Specification
"External Termination
10.
25. Updated I/O Test
section. Updated all
17. Updated
49. Corrected
36. Improved
Table
Table 38
19.
R