XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 59

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Byte Peripheral Interface (BPI) Configuration Timing
Table 53: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
DS529-3 (v1.5) July 10, 2007
Product Specification
T
T
T
T
T
T
T
T
(Open-Drain)
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
SMDCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
CCLK
D[7:0]
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
R
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK falling edge
Hold time on D[7:0] data inputs after CCLK falling edge
Figure 15: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
DC and Switching Characteristics
Minimum
New ConfigRate active
T
50
CCLK1
Address
0
5
0
T
CCO
Data
(see
(see
See
See
T
T
DCC
CCLKn
Maximum
Address
Table
Table
Table 49
Table 50
–
–
5
–
Data
45)
45)
DS529-3_05_112906
Address
T
T
cycles
Units
CCD
CCLK1
ns
ns
ns
Data
59