XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 35

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

The capacitive load (C
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V
with the parameters used in
not confuse V
model with V
table. A fourth parameter, C
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
2. Record the time to V
3. Simulate the same signal standard with the output
4. Record the time to V
5. Compare the results of steps 2 and 4. Add (or subtract)
DS529-3 (v1.5) July 10, 2007
Product Specification
L
value of zero. High-impedance probes (less than 1 pF)
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
driver connected to the test setup shown in
Use parameter values V
C
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V
and V
load.
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment
yield the worst-case delay of the PCB trace.
REF
is zero.
MEAS
R
REF
REF
REF
values) or capacitive value to represent the
, R
(the input-switching threshold) from the
(the termination voltage) from the IBIS
REF
L
) is connected between the output
, and V
M
MEAS
.
REF
Table 26
T
, R
.
MEAS
, is always zero. The four
T
, and V
) correspond directly
(V
REF
T
M
, R
from
, R
T
, and V
(Table
REF
Table
Figure
, C
M
25) to
REF
). Do
26.
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9.
,
DC and Switching Characteristics
35