XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 48

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Table 38: Switching Characteristics for the DFS (Continued)
Notes:
1.
2.
3.
4.
5.
6.
48
Lock Time
LOCK_FX
The numbers in this table are based on the operating conditions set forth in
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA.
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
(2, 3)
Symbol
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals are
valid. If using both the DLL and the DFS, use
the longer locking time.
Description
www.xilinx.com
F
5 MHz < F
CLKIN
< 15 MHz
Table 8
> 15 MHz
CLKIN
and
Device
Table
All
37.
Min
–
–
-5
Max
Speed Grade
450
DS529-3 (v1.5) July 10, 2007
5
Product Specification
Min
–
–
-4
Max
450
5
Units
ms
μs
R