dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 62

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
6.0 Hardware User Information
Symptoms:
An improper five bit PHY Address is latched into the
DP83840A upon power-on/reset.
Solution/Workaround:
In order to guarantee that a logic low level is latched-in to
PHYAD[3] upon power-up/reset, it is recommended that a
4.7k
ground. Figure 23 illustrates the recommended connection
of external circuitry when using PHYAD[3] / SPEED_100 to
control
implementations.
In order to guarantee that a logic high level is latched-in to
PHYAD[3] upon power-up/reset, it is recommended that a
1.0k
and that a 1.2k
this pin and the transistor control circuitry. It is important to
take note that the base resistor values (each 100
case) are lowered in order to compensate for the series
resistor be connected from this pin directly to Vcc
resistor be connected from this pin directly to
transistors
Figure 23. Recommended Control Circuitry and Valid PHYAD[3] Logic Low Latch-in Value
Figure 24. Recommended Control Circuitry and Valid PHYAD[3] Logic High Latch-in Val
PHYAD[3]/
SPEED_100
DP83840A
resistor be connected in series between
PHYAD[3]/
SPEED_100
DP83840A
used
for
Vcc
GND
Common
1.0 k
1.2k
100
4.7k
(Continued)
TXREF
1.2 k
Magnetics
Q1
in this
62
TXREF
100
1.2k
Figure 24 illustrates the recommended connection of
external circuitry when using PHYAD[3] / SPEED_100 to
control
implementations.
6.5 Collision De-Assertion Time
Problem:
In 100 Mb/s operation, the Collision De-Assertion time
violates the IEEE802.3u specification.
Description:
The Collision De-Assertion time which is determined from
when TX_EN is deasserted to COL going low is specified
at
22.2.4.1.9. This is a test mode function. The DP83840A
has a specification of 87ns maximum.
Q1
All resistors are 1/8th Watt, +/- 5% tolerance
40ns
TXO+ Term
All resistors are 1/8th Watt, +/- 5% tolerance
resistor with respect to proper transistor biasing.
transistors
1.2 k
Q2
maximum
National Semiconductor
TXO+ Term
100
Q2
used
per
TXO- Term
IEEE
for
1.2 k
Q3
Common
802.3u/D5.3
TXO- Term
Q3
ue
Magnetics
section