mc33351adtb ON Semiconductor, mc33351adtb Datasheet - Page 11

• Manufacturer Part Number: mc33351adtb
• Description: Lithium Battery Protection Circuit For Three Battery Packs
• Manufacturer: ON Semiconductor

by the values selected for the internal resistor divider string.
As the battery pack reaches full charge, the Cell Voltage
Detector will sense an overvoltage fault condition on the
first cell that exceeds the pre−set overvoltage limit. The fault
information is stored in a data latch and charge MOSFET Q1
is turned off, disconnecting the battery pack from the
charging source. An internal current source pull−up is then
applied to the lower tap of the divider when the overvoltage
cell is again sensed. This creates an input hysteresis voltage
with divider resistors R1 and R2. As a result of an
overvoltage fault, the battery pack is available for
discharging only.
battery pack. As the voltage across the highest voltage cell
falls below the hysteresis level, charge MOSFET Q1 will
turn on and the current source pull−up will turn off. The
battery pack will now be available for charging or
discharging.
the Cell Voltage Detector will sense an undervoltage fault
condition on the first cell that falls below the designed
undervoltage limit. After an undervoltage cell is detected,
undervoltage fault output goes low and discharge MOSFET
Q2 is turned off, disconnecting the battery pack from the
load after 16 seconds. The protection circuit will now enter
a low current sleepmode state drawing less than 15.0 nA
typically, thus preventing any further cell discharging. As a
result of the undervoltage fault, the battery pack is available
for charging only. An alternate method of turning discharge
MOSFET Q2 can be employed using R
in Figures 1 and 2. Recommended value of R
5.1 kW and 22 mfd respectively generates a time delay of 110
±10% milliseconds.
to the battery pack. When the voltage on Pin 8 exceeds
Pin 16 by 0.6 V, discharge MOSFET Q2 will be turned on.
The battery pack will now be available for charging or
discharging.
Cell Voltage Balancing
discharge cycles can result in a significant difference in cell
voltage with a corresponding degradation of battery pack
The cell charge and discharge voltage limits are controlled
The overvoltage fault is reset by applying a load to the
As the load eventually depletes the battery pack charge,
The undervoltage fault is reset by applying charge current
With series connected cells, successive charge and
Selector
Selector
From
Cell
Cell
To
Figure 13. Cell Voltage Limit Sampling
Cell Voltage
Over/Under
Reference
Detector
Floating
&
vs. Programming
Cell Voltage
Discharge Voltage
Threshold
Charge Voltage
Threshold
Cell Voltage
Return
T
and C
R1
R2
R3
T
T
and C
as shown
Voltage
Cell
http://onsemi.com
+
−
T
of
11
capacity. Figure 13 illustrates the operation of an
unbalanced three cell pack. As the cells become unbalanced,
the full battery pack capacity is not realized. This is due to
the requirement that charging must terminate when the
highest voltage cell reaches the overvoltage limit, and
discharging must terminate when the lowest voltage cell
reaches the undervoltage limit. By employing a method of
keeping the cell voltages equal, each of the cells can be
charged and discharged to their specified limits, thus
attaining the maximum possible capacity.
circuit that controls three internal MOSFETs. These
MOSFETs are connected to an external transistor and
resistor combination across the individual cells. The circuit
samples the voltage of each cell during the polling period. If
all of the cells are below the programmed overvoltage fault
limit, no cell balancing takes place. If one or more cells reach
the overvoltage fault limit, a specific latch is set for each cell.
At the end of the polling period, charge MOSFET Q1 is
turned off and the latches are interrogated. If all of the
latches were set, no cell balancing takes place. If one, two,
or three latches were set, the required cell balancing
MOSFETs are then activated. The overvoltage cells are
discharged to the pre−set level. As each cell attains this level,
the balancing MOSFETs successively turn off. Upon
completion of cell balancing, charge MOSFET Q1 is turned
on. Cell voltage balancing can be active during charging and
discharging, but is disabled during the low current
sleepmode state.
Test Mode
pack testing. By connecting Pin 2 to 3.0 V above V
internal logic is held in a reset state and both MOSFET
switches are turned on. Upon release, the Control Logic
becomes active and the cell are polled within 4.0 ms.
The MC33351A contains a Cell Voltage Balancing Logic
A test option is provided to speed up device and battery
Figure 14. Unbalanced Battery Pack Operation
Charged
Cell 3
Cell 2
Cell 1
4.2 V
Overvoltage
Limit
4.0 V
Disharge
Charge
2.5 V
Undervoltage
Limit
2.7 V
Discharged
Cell 3
Cell 2
Cell 1
C
the