lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 41

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK2
DATA REGISTER
data buffer byte/word presently addressed by
the pointer register.
This register is mapped into two uni-directional
FIFOs that allow moving words to and from the
LAN91C100 regardless of whether the pointer
address is even, odd or dword aligned. Data
goes through the write FIFO into memory, and
is pre-fetched from memory into the read FIFO.
(next) byte can be accessed through the Data
If byte accesses are used, the appropriate
8 THROUGH Bh
8
9
A
B
OFFSET
Used to read or write the
DATA REGISTER
NAME
41
Low or Data High registers. The order to and
from the FIFO is preserved.
dword accesses can be mixed on the fly in any
order.
This register is mapped into two consecutive
word locations to facilitate double word move
operations regardless of the actual bus width
(16 or 32 bits). The DATA register is accessible
at any address in the 8 through Ah range, while
the number of bytes being transferred are
determined by A1 and nBE0-nBE3. The FIFOs
are 12 bytes each.
DATA
DATA
DATA
DATA
READ/WRITE
TYPE
Byte, word and
SYMBOL
DATA