lan91c95 Standard Microsystems Corp., lan91c95 Datasheet
lan91c95
Related parts for lan91c95
lan91c95 Summary of contents
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... Handles Block Word Transfers for Any Alignment High Performance Chained ("Back-to- Back") Transmit and Receive Flat Memory Structure for Low CPU Overhead Dynamic Memory Allocation Between Transmit and Receive Buffered Architecture, Insensitive to Bus Latencies (No Overruns/Underruns) Supports Boot PROM for Diskless ISA Applications LAN91C95 ...
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FEATURES ........................................................................................................................................1 PIN CONFIGURATION.......................................................................................................................3 GENERAL DESCRIPTION .................................................................................................................4 OVERVIEW ........................................................................................................................................4 PIN REQUIREMENTS ........................................................................................................................7 DESCRIPTION OF PIN FUNCTIONS .................................................................................................9 BUFFER TYPES ..............................................................................................................................16 FUNCTIONAL DESCRIPTION..........................................................................................................20 MODEM INTERFACE ......................................................................................................................23 BUFFER MEMORY ..........................................................................................................................24 INTERRUPT STRUCTURE...............................................................................................................32 RESET LOGIC .................................................................................................................................33 POWERDOWN LOGIC.....................................................................................................................34 INTERNAL VS EXTERNAL ATTRIBUTE MEMORY ...
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... Uses Certified LAN9000 Drivers for Major Network Operating Systems Software Driver Compatible with LAN91C92, LAN91C94 and LAN91C100 (100 Mbps) and LAN91C110 (100 Mbps) Controllers in ISA Mode Software Driver Utilizes Full Capability of 32 Bit Microprocessor PIN CONFIGURATION LAN91C95 VSS 93 ...
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... PCMCIA interface, with independent decoders for the LAN and for the modem functions. These decoders LAN91C95 is used as a multi-function card, and they can be bypassed when only one function is enabled. The LAN91C95 also merges the LAN’s Mode internal interrupt source with the external modem interrupt connected to the LAN91C95 ...
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... To complement architecture, all ISA bus interface functions are incorporated in the LAN91C95, as well byte packet RAM and serial EEPROM-based setup. The user can select or modify configuration choices. The LAN91C95 stores ...
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... PCMCIA I/O ignores address lines A4-A15 and relies on the PCMCIA host, decoding for the slot nROM/nPCMCIA on the LAN91C95 is left open with a pullup for ISA mode. This pin is sampled at the end of Power On Reset. If found low, the LAN91C95 is configured for PCMCIA mode. 6 ...
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FUNCTION SYSTEM ADDRESS BUS SYSTEM DATA BUS SYSTEM CONTROL BUS MODEM INTERFACE SERIAL EEPROM PIN REQUIREMENTS ISA PCMCIA A0-A15 A0-A15 A16 nFWE A17 nFCS A18 A19 nCE1 nREG AEN D0-D15 D0-D15 RESET RESET BALE nWE nIORD nIORD nIOWR nIOWR nMEMR ...
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FUNCTION CRYSTAL OSC. POWER GROUND 10BASE-T INTERFACE AUI INTERFACE COLN TXP/nCOLL LEDs nRXLED/RXCLK MISC. PWRDWN/TXCLK TOTAL PINS ISA PCMCIA XTAL1 XTAL1 XTAL2 XTAL2 VDD VDD AVDD AVDD GND GND AGND AGND TPERXP TPERXP TPERXN TPERXN TPETXP TPETXP TPETXN TPETXN TPETXDP ...
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... DESCRIPTION I/O4 with This pin is sampled at the end of RESET. pullup When this pin is sampled low the LAN91C95 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode. For ISA operation this pin is left open and is used as a ROM chip select output that goes active when nMEMR is low and the address bus contains a valid ROM address ...
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... LAN91C95 to extend host cycles. PCMCIA - Output. Optionally used by the LAN91C95 to extend host cycles. I/O24 Bidirectional. 16 bit data bus used to access the LAN91C95 internal registers. The data bus has weak internal pullups. Supports direct connection to the system bus without external buffering. IS with Input ...
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... LAN91C95 address programmed into the high byte of the Base Address Register. PCMCIA - Active low output asserted whenever the LAN91C95 bit mode, and “Enable Function” bit in the ECOR register is high, nREG is low and A4-A15 decode to the LAN address specified in I/O Base Registers 0 and 1 in PCMCIA attribute space ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 24 nModem nMRESET Reset 18 Modem MINT Interrupt 23 nModem nMCS Chip Select 17 Modem MRDY Ready 27 nModem nMPWDN Powerdown 26 MIDLEN1 20 Modem Ring MRINGIN Input 21 nModem nMRINGOA Ring ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 15 Speaker SPKROUT Output 28 nMPDOUT 29 MFBK1 16 n16 Bit nMIS16 Modem 110 EEPROM EESK Clock 109 EEPROM EECS Chip Select 108 EEPROM EEDO/ Data Out SDOUT 107 EEPROM EEDI Data ...
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... EEPROM is used. I with pullup Input. When low the LAN91C95 is configured for 16 bit bus operation. If left open the LAN91C95 works in 8 bit bus mode. 16 bit configuration can also be programmed via serial EEPROM (In ISA Mode only) or via software initialization of the CONFIGURATION REGISTER ...
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... Used in combination with TPETXP and TPETXN to generate the 10BASE-T transmit pre-distortion. I with pullup Internal ENDEC - Powerdown input. It keeps the LAN91C95 in powerdown mode when high (open). Must be low for normal operation. Refer to the Powerdown Matrix following for further details. External ENDEC - Transmit clock input from ...
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... TYPE DESCRIPTION Analog Input A 39 kohm 1% resistor should be connected between this pin and analog ground. I with pullup When tied low the LAN91C95 is configured for external ENDEC. When tied high or left open the LAN91C95 encoder/decoder. +5V power supply pins +5V analog power supply pins ...
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... CABLE SIDE FIGURE 1 - LAN91C95 SYSTEM BLOCK DIAGRAM FOR ISA BUS WITH BOOT PROM AUI 17 ...
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... SPKROUT t o nOE r nFWE nFCS nOE nWE nCE Extended D0-7 Attribute A0-8 PROM 2816 (Optional) FIGURE 2 - LAN91C95 SYSTEM BLOCK DIAGRAM FOR DUAL FUNCTION PCMCIA CARD 10BASE-T / AUI INTERFACE MRDY RDY nIOWR , nMCS nCS nMRESET nRESET MINT INT 91C95 MRINGIN RING SPKRIN SPKR MRINGOnA/B ...
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... MODEM DATA INTERFACE BUS ADDRESS MANAGEMENT BUS BUS INTERFACE CONTROL FIGURE 3 - LAN91C95 INTERNAL BLOCK DIAGRAM ENDEC CSMA/CD ARBITER MMU TWISTED PAIR TRANSCEIVER RAM 19 AUI 10BASE-T ...
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... RAM for packet storage. This RAM buffer is accessed by the CPU through two sequential access regions of 3 kbytes each. The RAM access is internally arbitrated by the LAN91C95 and dynamically allocated between transmit receive packets using 256 byte pages. The Ethernet controller functionality is identical to the LAN91C94 except where indicated otherwise ...
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Table 2 - Bus Transactions In PCMCIA Mode 8 BIT MODE ((IOis8=1) + (nEN16=1).(16BIT=0)) 16 BIT MODE otherwise 16BIT = CONFIGURATION REGISTER bit 7 IOis8 = ECSR register bit 5 nEN16 = pin nEN16 For the modem function, the transactions ...
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... Space Ethernet I/O nIORD/nIOWR Space (1) (1) This space also allows access to the PCMCIA Configuration Register through Banks 4 and 5 (LAN91C95 only). Except for the bus interface, the functional behavior of the LAN91C95 after initial configuration is identical for ISA and PCMCIA modes. The LAN91C95 includes an arbitrated shared memory of 6 kbytes accessed by the CPU ...
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... It is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision detection as well as the link integrity test function. The LAN91C95 provides a 16 bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter. ...
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... The FIFO of packets, existing beneath the TX and RX areas, is managed by the MMU. The MMU dynamically allocates and releases memory to be packet used by the transmit and receive functions. The MMU related parameters for the LAN91C95 are: RAM size Max. number of packets Max. pages per packet Max ...
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RCV POINTER BIT REGISTER 11-BIT LOGICAL ADDRESS RCV VS. TX AREA SELECTION FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA TX PACKET NUMBER 2K TX MMU AREA RX PACKET NUMBER 2K RX MMU AREA 25 PHYSICAL MEMORY ...
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PACKET NUMBER REGISTER PACKET #A CPU SIDE TX FIFO PACKET #B CSMA TX COMPLETION FIFO PACKET #C FIFO PORTS REGISTER FIGURE 5 - TRANSMIT QUEUES AND MAPPING STATUS COUNT DATA STATUS COUNT DATA TO STATUS COUNT DATA LINEAR ADDRESS MMU ...
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FIFO PORTS REGISTER PACKET #D CPU SIDE RX FIFO PACKET #E FROM CSMA FIGURE 6 - RECEIVE QUEUE AND MAPPING STATUS COUNT DATA STATUS COUNT DATA LINEAR ADDRESS MMU MAPPING 27 MEMORY ...
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... FIGURE 7 - LAN91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH 28 ...
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PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the TRANSMIT and RECEIVE areas. The first word is reserved for the status word, the next word is bit15 ...
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... On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C95 treated transparently as data both for transmit and receive operations. CONTROL BYTE - The CONTROL BYTE always resides on the high byte of the last word ...
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RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory not available as a register. HIGH ALGN BROD BYTE ERR CAST LOW BYTE 5 ALGNERR - Frame had alignment error. BRODCAST ...
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... INTERRUPT STRUCTURE The LAN91C95 merges two main interrupt sources into a single interrupt line. One source is the Ethernet interrupt and the other is the modem interrupt. The Ethernet interrupt is conceptually equivalent to the LAN91C92 interrupt line the OR function of all enabled interrupts within the Ethernet core ...
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RESET LOGIC The pins and bits involved in the different reset mechanisms are: RESET - Input Pin TABLE 5 - RESET FUNCTIONS RESETS THE FOLLOWING FUNCTIONS RESET Pin All internal logic POR Circuit Generates an internal reset of at least ...
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POWERDOWN LOGIC The pins and bits involved in powerdown are: 1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0). 2. Pwrdwn bits in ECSR and MCSR registers - One bit for each function 3. Enable Function bits ...
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Table 6B - ISA MODE (*Rev. C and Higher) PWR DWN nWAKEUP- WAKES Pin EN PIN FUCNTIO UP BY (A=Assrtd) (A=Assrtd) N ENABLE PWRDWN change Pin deassertn nWAKEUP change -EN Pin deassertn - AND-, ...
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Table 7A - PCMCIA MODE (Refer to table 7B for next states to wake-up events) CURRENT STATE nWAKE PWRD UP-EN WN PIN ECOR ECSR Pin(A=A (A=Assr FUNC PWR No. ssrtd) td) ENABLE DOWN ...
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Table 7B - PCMCIA MODE (*Rev. C and Higher) PWR nWAKE DWN UP-EN Pin PIN ECOR WAKES UP (A=Ass (A=Ass FUNC BY rtd) rtd) ENABLE PWRDWN Pin deassertn change nWAKEUP Pin change deassertn ...
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PWR nWAKE DWN UP-EN Pin PIN ECOR WAKES UP (A=Ass (A=Ass FUNC BY rtd) rtd) ENABLE By writing ECSR Power Down taking the chip out of MP mode by writing WAKEUP_EN = 0 By writing ...
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Table 8A - Effect of STSCHG_SLCT Bit in CR/Refer to table 8B for next states to wake-up CURRENT STATE MCOR MCSR CR FUNC PWR STSCHG_ ENABLE DOWN SLCT BIT No BIT BIT (New ...
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... EEPROM device when using up to 512 bytes of “Card Information” and, if additional memory is needed, an external EEPROM may be used. When the LAN91C95 goes into powerdown mode, the internal CIS data buffer RAM is re- initialized. The LAN91C95 generates the appropriate control ...
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... PCMCIA Configuration Registers: Address 8000-803Eh The PCMCIA Configuration Registers are stored inside the LAN91C95 above the external Attribute Memory address space. These registers are used to configure and control the PCMCIA related functionality of the Ethernet and Modem functions. INTERNAL SRAM ...
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PCMCIA CONFIGURATION REGISTERS DESCRIPTION Ethernet Function (Base Address 8000h) 8000h - Ethernet Configuration Option Register (ECOR SRESET LevIREQ BIT 7 - SRESET: This bit when set will clear all internal registers associated with the ...
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... IOIs16 signal. BIT 4 - Not defined BIT 3 - Not defined BIT 2 - PwrDwn: When set (1), this bit puts the LAN91C95 Ethernet function into powerdown mode. The Ethernet function is also put into powerdown mode when the Enable Function bit (ECOR bit 0) is cleared. Refer to the Powerdown Logic section for additional details as to what logic is powered down ...
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I/O Base Register 0 & 1 (I/O Base 0 & 1) Address 800Ah & 800Ch 800Ah - Ethernet I/O BASE Register 800Ch - Ethernet I/O BASE Register ...
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... PCMCIA functionality, this bit must be set. BIT 0 - Enable Function: This bit enables (1) or disables (0) the Modem function. While the Modem is disabled the LAN91C95 inhibits nMCS, IREQ is not generated for the Modem function and nINPACK is not returned for accesses to the Modem registers. ...
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Modem Configuration and Status Register (MCSR) Address 8022h Changed SigChg IOIs8 Bit 7 - Changed: This bit is the logical OR of the CREADY/-Bsy and (RINGEVENT bit logically anded with RINGENABLE) states. ...
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Pin Replacement Register (PRR Cready/ -Bsy Cready/-Bsy: This bit is set to a one when the bit Rready/-Bsy bit changes state from zero(0) to one (1) or one (1) to zero (0) ...
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Extended Status Register(ESR RINGEVENT RINGEVENT: This bit is latched to a one at the start of each ring frequency cycle (input from ring input from modem, the MRINGIN signal going high). When ...
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Modem I/O BASE Register 802Ch - Modem I/O BASE Register A15 A14 A13 The Modem I/O Base registers determine the base ...
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... Register (either reset or serial EEPROM default in ISA mode only). The Ethernet I/O space can be configured bit space, and is similar to the LAN91C95, LAN91C92, etc. I/O space. To limit the I/O space requirements to 16 locations, the registers are split into six banks. The last word of the I/O area is shared by all banks and can be used to change the bank in use ...
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... Interrupt Mask) are functionally described as two eight bit registers; in that case the offset of each one is independently specified. Regardless of the functional description, when the LAN91C95 bit mode, all registers can be accessed as words or bytes. The default bit values upon hard reset are highlighted below each register. ...
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BANK0 BANK1 0 TCR CONFIG 2 EPH STATUS BASE 4 RCR IA0-IA1 6 COUNTER IA2-IA3 8 MIR IA4-IA5 A MCR GENERAL PURPOSE C RESERVED CONTROL (0) E BANK BANK SELECT SELECT TABLE 11 - Internal I/O Space Map BANK2 BANK3 ...
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... Res. Res. Res. BS2 The BANK SELECT REGISTER is always accessible regardless of the value of BS0-BS2. The LAN91C95 implements only four banks in ISA mode, therefore, accesses to non-existing banks (BS2=1) are ignored. All six banks are accessible in PCMCIA mode. BS1 BS0 BANK ...
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... CRC. Defaults to zero, namely CRC an inserted. PAD_EN - When set, the LAN91C95 will pad transmit frames shorter than 64 bytes with 00. Does not pad frames when reset. FORCOL - When set, the transmitter will force a collision by deliberately not deferring. After the collision, this bit is automatically reset ...
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... TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared, the LAN91C95 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. LOOP LOOPS EPH Block 0 1 ENDEC ...
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I/O SPACE - BANK0 OFFSET NAME 2 EPH STATUS REGISTER This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to ...
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QFP) or WAKEUP_EN in CTR. Note: If the MP mode is activated using the nWAKEUPEN pin, the pin must be deasserted to exit the mode. TX_DEFR - Transmit Deferred. When set, carrier ...
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... SOFT_RST - Software activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C95 configuration is not preserved, except for Configuration, Base, and IA0-IA5 Registers. The EEPROM in both ISA and PCMCIA mode is not reloaded after software reset ...
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I/O SPACE - BANK0 OFFSET NAME 6 COUNTER REGISTER Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do not wrap around beyond 15. HIGH ...
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... LAN91C100 TYPE READ ONLY MEMORY SIZE (IN BYTES *256 * MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H (6144 bytes) for the LAN91C95. M ACTUAL MEMORY FFH 1 40H 1 12H 1 18H 1 FFH 2 60 ...
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I/O SPACE - BANK0 OFFSET NAME A MEMORY CONFIGURATION REGISTER HIGH BYTE 0 0 LOW MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M) BYTE 0 0 MEMORY RESERVED FOR TRANSMIT Programming this value allows the host CPU to ...
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... An exception to this are accesses to the Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three 20 MHz clocks on any cycle to the LAN91C95. STSCHG_SLCT(*) - PCMCIA mode only. STSCHG_SLCT low (0), Modem Function Enable bit = 0, in MCOR, it does not allow any events (such as Ring In reported to the host via the nSTSCHG Pin assertion ...
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... LAN91C95 disables link test functions by not generating nor monitoring the network for link pulses. In this mode the LAN91C95 will transmit packets regardless of the link test, the EPHSR LINK_OK bit will be set and the LINK LED will stay on. When low the link test functions are enabled. If ...
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... ISA mode against the I/O address on the bus to determine the IOBASE for LAN91C95 registers. The 64k I/O space is fully decoded by the LAN91C95 down location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros. ROM SIZE - Determines the ROM decode area in ...
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... IEEE Ethernet Address stored in the EEPROM. Once this data is stored in the CIS SRAM data buffer in the LAN91C95 parsed by the host to extract the IEEE Address information and stored manualy by the LAN Driver. Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable ...
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... Store operations. This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C95. 66 SYMBOL GPR ...
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... When clear bad CRC packets do not generate interrupts and their memory is released. PWRDN - Active high bit used to put the Ethernet function in powerdown mode. Cleared by write to any register in the LAN91C95 I/O space 2. Hardware reset 3. “Magic Packet” was received This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to determine when the function is powered down ...
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... This bit then Clears upon completing the operation. In PCMCIA Mode: The LAN91C95 reads the contents of the EEPROM and stores the contents in the LAN91C95 CIS SRAM as defined in Table 12. STORE In ISA Mode: The STORE bit when set, stores the contents of all relevant registers in the serial EEPROM ...
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... Note: This memory map assumes a 4096 bit Serial EEPROM in PCMCIA mode. Table 12 - EEPROM ADDRESS IN WORDS Word 1 - Low Byte Word 1 - High Byte Word 2 - Low Byte Word 2 - High Byte .. .. Word FE - Low Byte Word FE- High Byte Word FF - Low Byte Word FF - High Byte 69 LAN91C95 SRAM IN BYTES Byte 0 Byte1 Byte2 Byte3 .. Byte FC Byte1FD Byte1FE Byte1FF ...
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I/O SPACE - BANK2 OFFSET NAME 0 MMU COMMAND REGISTER This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: ...
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ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. 111 7) RESET TX FIFOs ...
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I/O SPACE - BANK2 OFFSET NAME 2 PACKET NUMBER REGISTER PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the ...
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I/O SPACE - BANK2 OFFSET NAME 4 FIFO PORTS REGISTER This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read ...
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I/O SPACE - BANK2 OFFSET NAME 6 POINTER REGISTER HIGH AUTO RCV BYTE INCR LOW BYTE 0 0 POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive areas. ...
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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C95 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers ...
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I/O SPACE - BANK2 OFFSET NAME C INTERRUPT STATUS REGISTER Res. ERCV INT EPH INT OFFSET C INTERRUPT ACKNOWLEDGE REGISTER Res. ERCV INT Res. OFFSET NAME D INTERRUPT MASK REGISTER Res. ERCV INT EPH INT X 0 ...
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The RX_OVRN INT bit, however, latches the overrun condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the RX_OVRN INT ...
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INT FIGURE 9 - INTERRUPT STRUCTURE 78 ...
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I/O SPACE - BANK 3 OFFSET NAME 0 THROUGH 7 MULTICAST TABLE LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 ...
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I/O SPACE - BANK3 OFFSET NAME 8 MANAGEMENT INTERFACE HIGH BYTE 0 0 LOW BYTE 0 0 nXNDEC - Read only bit reflecting the status of the nXENDEC pin. IOS0-IOS2 - Read only bits reflecting the status of the IOS0-IOS2 ...
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... LOW CHIP BYTE 0 1 CHIP - Chip ID. Can be used by software drivers to identify the device used. CHIP ID VALUE TYPE READ ONLY REV - Revision ID. Incremented for each revision of a given device. DEVICE 3 LAN91C90/LAN91C92 4 LAN91C94 5 LAN91C95 7 FEAST 81 SYMBOL REV REV ...
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I/O SPACE - BANK 3 OFFSET NAME C EARLY RCV REGISTER HIGH BYTE 0 0 LOW RCV BYTE DISCRD 0 0 RCV DISCRD - Set to discard a packet being received. This bit can be used in conjunction with ERCV ...
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... Headers can be analyzed without reading the entire packet. The packet can be read or written with a block move operation. Multiple upper layer support - The LAN91C95 facilitates interfacing to multiple upper layer protocols because of ...
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Behavior in FDSE Mode The main 802.3 section affected by FDSE is 4.2.8 where the Frame Transmission procedural model is presented. The changes are deferral - The transmit channel is dedicated and always available - The device will ...
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TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL CODE - Poll until the ALLOC INT bit is ...
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TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 ENABLE RECEPTION - By setting the RXEN bit SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet ...
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ISR Save Bank Select & Address Ptr Registers Mask 91C94 Interrupts Read Interrupt Register Y es Call TX INTR or TXEMPTY INTR Get Next TX ALLOC INTR? Packet No Available for Transmission Call ALLOCATE EPH INTR? Y ...
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FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU 88 ...
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RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Destination Yes No Multicast? Read Words from RAM for Address Filtering No Yes Address Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get ...
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...
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Write Acknowledge Reg. with TXEMPTY Bit Set & ...
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DRIVER SEND Choose Bank Select Register 2 Call ALLOCATE Exit Driver Send Yes Read Allocation Result Register Write Allocated Packet into Packet # Register Write Address Pointer Register Copy Part of TX Data Packet into RAM Write Source Address into ...
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... PCMCIA card needs less than 512 bytes of configuration information. As can be seen in the map, if 512 bytes of CIS or less is required, the nFCS and nFWE output pins of the LAN91C95 need not be used (if serial EEPROM is being used). Internal to the LAN91C95, the memory addressing logic will allow byte or word access on even byte boundaries ...
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TABLE 13 - ATTRIBUTE MEMORY DECODES USING SERIAL EPROM ATTRIBUTE EXTERNAL EPROM MEMORYADDRESS 0 - 3FEh 400h-7FFEh 8000h - 803Eh TABLE 14 - ATTRIBUTE MEMORY DECODES WITHOUT SERIAL EPROM ATTRIBUTE EXTERNAL EPROM MEMORYADDRESS 0 - 7FFEh 8000h - 803Eh INTERNAL ...
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... TX DONE PACKET NUMBER at the FIFO PORTS register. eliminates the need for the driver to keep a list of packet numbers being transmitted. numbers are queued by the LAN91C95 and provided back to the CPU as their transmission completes. 2) One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1 ...
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Typically there would be three processes using the pointer: 1) Transmit loading (sometimes driven) 2) Receive unloading (interrupt driven) 3) Transmit Status reading (interrupt driven) 1) and 3) also share the usage of the Packet interrupt Number Register. restoring the ...
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FUNCTIONAL DESCRIPTION OF THE BLOCKS MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and de- allocation, it interfaces the arbiter only. The ...
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... BASE ADDRESS REGISTER, requiring that AEN be low. If the above address comparison is satisfied and the LAN91C95 bit mode, nIOCS16 will be asserted (low). A valid comparison does not yet indicate a valid I/O cycle is in progress, as the addresses could be used for a memory cycle, or could even glitch through a valid value ...
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... I/O access to the LAN91C95 + one clock for the memory cycle clocks. In absolute time it means 375ns for a 8MHz bus, and 240ns for a 12.5 MHz bus. The cycle time will not increase when configured ...
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... The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of packets the LAN91C95 can handle (18). The guideline is software transparency; the software driver should not be aware of different devices or FIFO depths ...
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FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS 101 ...
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... CSMA/CD block. A packet will be received if the destination address is broadcast addressed to the individual address of the LAN91C95 multicast address and ALMUL bit is set multicast address matching one of the multicast table entries. If the PRMS bit is set, all packets are received. ...
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... Link_loss_timer Link_test_min_timer Link_count Link_test_max_timer The state of the link is reflected in the EPHSR. AUI The LAN91C95 also provides a standard 6 wire AUI interface to a coax transceiver. PHYSICAL INTERFACE The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T transceiver. ...
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Transmit Functions Manchester Encoding The PHY encodes the transmit data received from the MAC. The encoded data is directed internally to the selected output driver for transmission over the twisted-pair network or the AUI cable. Data transmission and encoding is ...
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Reverse Polarity Function In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. Collision Detection Function In the 10BASE-T mode, while in half duplex, a collision state is ...
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... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C95. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, ...
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... When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C95 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. ...
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For example odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately a full word is completing three bytes into the FIFO. If the CPU reads a word, one byte will be left ...
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IOS2 ...
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... Note: This memory map assumes a 4096 bit Serial EEPROM in PCMCIA mode. Table 15 - EEPROM ADDRESS IN WORDS Word 1 - Low Byte Word 1 - High Byte Word 2 - Low Byte Word 2 - High Byte .. .. Word FE - Low Byte Word FE- High Byte Word FF - Low Byte Word FF - High Byte 110 LAN91C95 SRAM IN BYTES Byte 0 Byte1 Byte2 Byte3 .. Byte FC Byte1FD Byte1FE Byte1FF ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range........................................................................................0 Storage Temperature Range .....................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................. +325 Positive Voltage on any pin, with respect to Ground ............................................................Vcc + 0.3V Negative Voltage on any pin, with respect to ...
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PARAMETER SYMBOL I Input Buffer CLK V Low Input Level ILCK V High Input Level IHCK Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage IH IP Type Buffers ...
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PARAMETER SYMBOL OD16 Type Buffer V Low Output Level OL I Output Leakage OL OD162 Type Buffer V Low Output Level OL V High Output Level OH I Output Leakage OL OD24 Type Buffer V Low Output Level OL I ...
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PARAMETER Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output Voltage (R=78 ...
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... Access Time t3 nCE1 Access Time t4 nOE Access Time t5 Output Disable Time from nCE1 high t6 Output disable Time from nOE high NOTE: Applies only when nWAIT is asserted by the LAN91C95. FIGURE 18 - PCMCIA MEMORY READ TIMING TIMING DIAGRAMS max DATA VALID Typ Min ...
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... Data to nWE High Setup Time t6 Data Hold Time from nWE High t7 Write Recovery Time (Address, nREG Hold from nWE High) NOTE: Minimum write pulse width must be met whether or not nWAIT is asserted by the LAN91C95 FIGURE 19 - PCMCIA MEMORY WRITE TIMING 250 min t4 20 min t3 t1 ...
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A[15:0] nMCS t15 t3 nREG t2 nCE t16 nIORD t1 nINPACK nIOIS16 t12 D[15::0] t10 t17 t9 t4 t11 t8 t13 FIGURE 20 - I/O READ TIMING (Table on the following page) 117 t18 t5 t20 t7 t19 t6 t36 ...
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PARAMETER t1 Address setup before nIORD low t2 nCEI, nCE2 setup before nIORD low t3 nREG setup before nIORD low t4 nIORD low width t5 Address hold from nIORD high t6 nCE1, nCE2 hold following nIORD high t7 nREG hold ...
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A[15:0] nMCS t30 t23 nREG t32 t22 nCE1 t31 nCE2 nIOWR t21 nIOIS16 t28 D[15::0] FIGURE 21 - (I/O WRITE TIMING) t27 t26 t24 (Table on the following page) 119 t33 t25 t35 t34 t36 t29 ...
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PARAMETER t21 Address setup before nIOWR low t22 nCE1, nCE2 setup before nIOWR low t23 nREG setup before nIOWR low t24 nIOWR low width t25 Address hold from nIOWR high t26 nCE1, nCE2, hold following nIOWR high t27 nREG hold ...
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A0-9,A15 valid t62 nREG t64 nCE1 t57 nWE nOE D0-7 valid Parameter t57 Write Data Setup to nWE Rising t58 Write Data Hold after nWE Rising t59 nOE Low to Valid Data t60 Address, nREG Setup to nWE Active ...
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A0-9,A15 valid t48 nREG t49 nCE1,nCE nIORD t47 D0-15 t46 nINPAC Parameter t46 nIORD Delay to t47 nREG Low to Control t48 nCE1,nCE2 Setup to Control t20 Cycle Time (No Wait t49 nREG Hold after Control t50 nCE1,nCE2 Hold ...
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A0-9,A15 valid t47 nREG t48 nCE1,nCE2 t54 nIOWR valid D0-15 Parameter nREG Low Setup to Control Active t47 nCE1,nCE2 Setup to Control Active t48 nREG Hold after Control Inactive t49 nCE1,nCE2 Hold after Control Inactive t50 Address Setup to ...
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A0-9,A15 valid nREG nCE1 t67 t67 t67 nFCS nWE t66 nFWE nOE Parameter t66 nWE to nFWE Delay t67 Address, nREG, nCE1 Delay to nFCS FIGURE 25 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0) valid t67 t67 t67 t67 t67 t67 ...
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MRINGOUTB t1 Parameter t1 MRINGOUTB Pulse Entering Powerdown t2 MRINGOUTB Pulse Exiting Powerdown FIGURE 26 - RINGOUT FOR L39/C39 ROCKWELL MODEMS ENTERING/EXITING POWERDOWN Min Typ Max 7.5 7.5 125 t2 Units ms ms ...
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A0-15 AEN, nSBHE VALID ADDRESS t15 nIOCS16 t3 nIORD t5 D0-15 Parameter t3 Address, nSBHE, AEN Setup to Control Active t4 Address, nSBHE, AEN Hold after Control Inactive t5 nIORD Low to Valid Data t6 nIORD High to Data Floating ...
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A0-15 AEN, nSBHE VALID ADDRESS t15 nIOCS16 t3 nIOWR VALID DATA IN D0-15 Parameter t3 Address, nSBHE, AEN Setup to Control Active t4 Address, nSBHE, AEN Hold after Control Inactive t7 Data Setup to nIOWR Rising t8 Data Hold after ...
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A0-15 AEN, VALID ADDRESS nSBHE nIOCS16 nIORD nIOWR t9 Z t10 IOCHRDY Z D0-D15 Parameter t9 Control Active to IOCHRDY Low t10 IOCHRDY Low Pulse Width* t20 Cycle time** *Note: Assuming NO WAIT configuration register and ...
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A0-15 (ISA) AEN, nSBHE nIOCS16 nIORD Z IOCHRDY D0-D15 Parameter t9 Control Active to IOCHRDY Low t18 IOCHRDY Width when Data is Unavailable at Data Register t19 Valid Data to IOCHRDY Inactive IOCHRDY is used instead of meeting t20 and ...
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A0-15 (ISA) AEN, nSBHE nIOCS16 nIOWR Z IOCHRDY D0-D15 Parameter t9 Control Active to IOCHRDY Low t18 IOCHRDY Width when Data Register is Full IOCHRDY is used instead of meeting t20 and t44. 'No Wait St' bit ...
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A0-15 VALID ADDRESS (ISA) AEN nIOWR t3 nIORD t5 Z VALID DATA OUT D0-7 Parameter t3 Address, nSBHE, AEN Setup to Control Active t5 nIORD Low to Valid Data t7 Data Setup to nIOWR Rising t8 Data Hold after nIOWR ...
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AEN A0-15, VALID nSBHE t1 t2 BALE t15 nIOCS16 t3 nIORD nIOWR Parameter t1 Address, nSBHE Setup to BALE Falling t2 Address, nSBHE Hold after BALE Falling t3 Address, nSBHE, AEN Setup to Control Active t4 AEN Hold after Control ...
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A0-19 VALID t1 BALE t3 nMEMRD nROM Parameter t1 Address Setup to BALE Falling t2 Address Hold after BALE Falling t3 Address Setup to Control Active t16 nMEMRD Low to nROM Low t17 nMEMRD High to nROM High FIGURE 35 ...
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EESK EEDO EEDI EECS t21 Parameter t21 EESK Falling to EEDO, EECS Changing 9346 is typically the serial EEPROM used. FIGURE 36 - EEPROM READ t21 min typ max 0 100 134 units ns ...
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EESK EEDI EECS t21 Parameter t21 EESK Falling to EEDO, EECS Changing 9346 is typically the serial EEPROM used. FIGURE 37 - EEPROM WRITE min typ max 100 135 t21 units ns ...
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POINTER ADDRESS REGISTER nIOWR nIORD IOCHRDY/ nWAIT (Z) Parameter t44 Pointer Register Reloaded to a Word of Data Prefetched into Data Register Note: If t44 is not met, IOCHRDY will be negated for the required time. This parameter can be ...
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TXD TXCLK t22 Parameter t22 TXD, nTXEN Delay from TXCLK Falling FIGURE 40 - EXTERNAL ENDEC INTERFACE - START OF TRANSMIT t23 RXD RXCLK nCRS Parameter t23 nCRS, RXD Setup to RXCLK Falling t24 nCRS, RXD Hold after RXCLK ...
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TPETXP t31 TPETXN t32 TPETXDN t33 TPETXDP TXP t34 TXN Parameter t31 TPETXP to TPETXN Skew t32 TPETXP(N) to TPETXDP(N) Delay t33 TPETXDN to TPETXDP Skew t34 TXP to TXN Skew FIGURE 42 - DIFFERENTIAL OUTPUT SIGNAL TIMING (10BASE-T AND ...
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RECP RECN t35 nCRS (internal) t36 1 0 TPERXP(N) t37 nCRS (internal) t38 Parameter t35 Noise Pulse Width Reject (AUI) t36 Carrier Sense Turn On Delay (AUI) t37 Noise Sense Pulse Width Reject (10BASE-T) t38 Carrier Sense Turn ...
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TPERXP TPERXN RECP RECN nCRS (internal) Parameter t39 Receiver Turn Off Delay FIGURE 44 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T) t39 min typ max 200 300 140 units ns ...
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TPETXP TPETXN b a TXP TXN Parameter t40 Transmit Output High to Idle in Half-Step Mode t41 Transmit Output High before Idle in Half-Step Mode FIGURE 45 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T) t40 t41 last ...
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COLLP COLLN t42 COL (internal) Parameter t42 Collision Turn On Delay t43 Collision Turn Off Delay FIGURE 46 - COLLISION TIMING (AUI) t43 min typ max 50 350 142 units ns ns ...
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MILLIMETER SYMBOL MIN. NOM. MAX. MIN 0.05 0.10 0.15 0.002 A 0.95 1.00 1.05 0.037 2 b 0.13 0.18 0.23 0.005 c 0.09 0.20 0.004 D 13.90 14.00 14.10 0.547 E 13.90 ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. CORRECTION REVISED Section added to data sheet Tables added to data sheet See Italicized Text See Italicized Text LAN91C95 Rev. 07/04/97 DATE 7/4/97 7/4/97 7/4/97 7/4/97 ...