lan9303 Standard Microsystems Corp., lan9303 Datasheet - Page 119

• Manufacturer Part Number: lan9303
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Single Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
8.5.2.1
8.5.3
S
S
A
6
S
A
5
Control Byte
S
A
4
S
A
3
S
S
A
2
S
A
6
S
A
1
S
A
5
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the
first three bytes of the register, the device will stop sending subsequent bytes. If the master sends an
unexpected start or stop condition, the device will stop sending immediately and will respond to the
next sequence as needed.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read (master sends a
no-acknowledge on one of the first three bytes or a start or stop condition occurs unexpectedly), the
read is considered invalid and the register is not affected. Multiple registers may be cleared in a
multiple read cycle, each one being cleared as it is read. I
return all zeros.
Figure 8.9
Control Byte
I
During reset, the I
is complete, the
read, the interface can be considered functional. At this point, the
Hardware Configuration Register (HW_CFG)
is complete. Refer to
I
Following the device addressing, as detailed in
the master continues to send data bytes. Each byte is acknowledged by the device. Following the
fourth byte of the sequence, the master may either send another start condition or halt the sequence
with a stop condition. The internal register address is unchanged following a single write.
Multiple writes are performed when the master sends additional bytes following the fourth
acknowledge. The internal address is automatically incremented and the next register is written. once
the internal address reaches it maximum value, it rolls over to 0. The multiple write is concluded when
the master sends another start condition or stop condition. The internal register address is incremented
for each write including the final. This is not relevant for subsequent writes, since a new register
address would be included on a new write cycle. However, this does affect the internal register address
if it were to be used for reads without first resetting the register address.
For both single and multiple writes, if the master sends an unexpected start or stop condition, the
device will stop immediately and will respond to the next sequence as needed.
The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written
(master sends a start, or a stop condition occurs unexpectedly), the write is considered invalid and the
S
A
0
2
2
S
A
4
C Slave Read Polling for Reset Complete
C Slave Write Sequence
0
S
A
3
A
C
K
S
A
2
A
9
S
A
1
A
8
Address Byte
S
A
0
A
7
illustrates a typical single and multiple register read.
0
A
6
C
A
K
A
5
A
9
A
4
Byte Order Test Register (BYTE_TEST)
Address Byte
A
8
A
3
2
A
7
C slave interface will not return valid data. To determine when the reset condition
A
2
A
6
A
C
K
Section 4.2, "Resets," on page 42
A
5
S
A
4
S
A
6
A
3
S
A
5
Control Byte
A
2
Figure 8.9 I
S
A
4
A
C
K
S
A
3
S
S
A
2
S
A
6
DATASHEET
S
A
1
S
A
5
Multiple Register Reads
Control Byte
Single Register Read
S
A
0
R/~W
S
A
4
1
S
A
3
A
C
K
2
119
S
A
2
C Slave Reads
D
3
1
Data 1 Byte
S
A
1
D
3
0
can be polled to determine when the device initialization
S
A
0
.. .
R/~W
1
Section
A
C
K
D
2
5
D
3
1
D
2
4
D
3
0
A
C
K
Data Byte
D
2
9
.. .
8.5.1, a register is written to the device when
...Data m Byte
for additional information.
should be polled. Once the correct pattern is
D
2
8
2
S
2
7
D
4
C reads from unused register addresses
D
2
6
D
3
D
2
5
D
2
D
2
4
D
1
A
C
K
Device Ready (READY)
D
0
D
2
3
Data Byte...
A
C
K
D
2
2
D
3
1
Data m+1 Byte... ...Data n Byte
D
2
1
D
3
0
D
2
0
D
2
9
.. .
D
2
8
...Data Byte
D
2
7
D
5
Revision 1.3 (08-27-09)
D
2
6
D
4
.. .
D
3
D
2
D
1
D
4
D
D
0
3
A
C
K
D
2
bit in the
P
D
1
D
0
A
C
K
P