lan9303 Standard Microsystems Corp., lan9303 Datasheet - Page 44

• Manufacturer Part Number: lan9303
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Single Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-27-09)
4.2.2
4.2.2.1
4.2.3
4.2.3.1
A nRST pin reset typically takes approximately 760uS, plus an additional 91uS per byte of data loaded
from the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in
approximately 6.0 seconds.
Note: The nRST pin is pulled-high internally. If unused, this signal can be left unconnected. Do not
Please refer to
Multi-Module Resets
Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration
straps are not latched upon multi-module resets. A multi-module reset is initiated by assertion of the
following:
Multi-module reset/configuration completion can be determined by first polling the
Register
Once the returned data is the correct byte ordering value, the serial interface resets have completed.
The completion of the entire chip-level reset must then be determined by polling the
(READY)
Ready (READY)
With the exception of the
(BYTE_TEST), and
forbidden while the
Device Ready (READY)
Note: The digital reset does not reset register bits designated as NASR.
Digital Reset (DIGITAL_RST)
A digital reset is performed by setting the
Register
PHY, Port 2 PHY, and Virtual PHY). The EEPROM Loader will automatically run following this reset.
Configuration straps are not latched as a result of a digital reset.
A digital reset typically takes approximately 760uS, plus an additional 91uS per byte of data loaded
from the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in
approximately 6.0 seconds.
Single-Module Resets
A single-module reset will reset only the specified module. Single-module resets do not latch the
configuration straps or initiate the EEPROM Loader. A single-module reset is initiated by assertion of
the following:
Port 2 PHY Reset
A Port 2 PHY reset is performed by setting the
Register (RESET_CTL)
(PHY_BASIC_CONTROL_x). Upon completion of the Port 2 PHY reset, the
(PHY2_RST)
are affected by this reset.
Digital Reset (DIGITAL_RST)
Port 2 PHY Reset
Port 1 PHY Reset
Virtual PHY Reset
rely on internal pull-up resistors to drive signals external to the device.
(BYTE_TEST). The returned data will be invalid until the serial interface resets are complete.
(RESET_CTL). A digital reset will reset all sub-modules except the Ethernet PHYs (Port 1
bit of the
and
Section Table 3.7, "Miscellaneous Pins," on page 38
bit indicates that the reset has completed and the device is ready to be accessed.
Reset (PHY_RST)
Hardware Configuration Register (HW_CFG)
Device Ready (READY)
Reset Control Register
or the
bit is set.
Hardware Configuration Register
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Reset (PHY_RST)
DATASHEET
bits are automatically cleared. No other modules of the device
44
(RESET_CTL), read access to any internal resources is
bit is cleared. Writes to any address are invalid until the
Digital Reset (DIGITAL_RST)
Port 2 PHY Reset (PHY2_RST)
bit in the (x=2)
(HW_CFG),
until it is set. When set, the
Port x PHY Basic Control Register
for a description of the nRST pin.
Byte Order Test Register
bit of the
SMSC LAN9303/LAN9303i
bit of the
Port 2 PHY Reset
Byte Order Test
Reset Control
Device Ready
Reset Control
Datasheet
Device